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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12-TRUE16 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12-FAKE16 %s6 7define half @swap(half %a, half %b, i32 %i) {8; GFX11-TRUE16-LABEL: swap:9; GFX11-TRUE16: ; %bb.0: ; %entry10; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l12; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l13; GFX11-TRUE16-NEXT: s_mov_b32 s0, 014; GFX11-TRUE16-NEXT: .LBB0_1: ; %loop15; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=116; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v217; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)18; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l19; GFX11-TRUE16-NEXT: v_swap_b16 v0.l, v0.h20; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v221; GFX11-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s022; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)23; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s024; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB0_125; GFX11-TRUE16-NEXT: ; %bb.2: ; %ret26; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s027; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]28;29; GFX11-FAKE16-LABEL: swap:30; GFX11-FAKE16: ; %bb.0: ; %entry31; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)32; GFX11-FAKE16-NEXT: s_mov_b32 s0, 033; GFX11-FAKE16-NEXT: .LBB0_1: ; %loop34; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=135; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)36; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v2, -1, v237; GFX11-FAKE16-NEXT: v_swap_b32 v1, v038; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v239; GFX11-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s040; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)41; GFX11-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s042; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB0_143; GFX11-FAKE16-NEXT: ; %bb.2: ; %ret44; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s045; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, v146; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]47;48; GFX12-TRUE16-LABEL: swap:49; GFX12-TRUE16: ; %bb.0: ; %entry50; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x051; GFX12-TRUE16-NEXT: s_wait_expcnt 0x052; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x053; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x054; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x055; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l56; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l57; GFX12-TRUE16-NEXT: s_mov_b32 s0, 058; GFX12-TRUE16-NEXT: .LBB0_1: ; %loop59; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=160; GFX12-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v261; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)62; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l63; GFX12-TRUE16-NEXT: v_swap_b16 v0.l, v0.h64; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v265; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)66; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s067; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)68; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s069; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB0_170; GFX12-TRUE16-NEXT: ; %bb.2: ; %ret71; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s072; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]73;74; GFX12-FAKE16-LABEL: swap:75; GFX12-FAKE16: ; %bb.0: ; %entry76; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x077; GFX12-FAKE16-NEXT: s_wait_expcnt 0x078; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x079; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x080; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x081; GFX12-FAKE16-NEXT: s_mov_b32 s0, 082; GFX12-FAKE16-NEXT: .LBB0_1: ; %loop83; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=184; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v2, -1, v285; GFX12-FAKE16-NEXT: v_swap_b32 v1, v086; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)87; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v288; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)89; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s090; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)91; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s092; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB0_193; GFX12-FAKE16-NEXT: ; %bb.2: ; %ret94; GFX12-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s095; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, v196; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]97entry:98 br label %loop99 100loop:101 %x = phi half [%a, %entry], [%y, %loop]102 %y = phi half [%b, %entry], [%x, %loop]103 %i2 = phi i32 [%i, %entry], [%i3, %loop]104 105 %i3 = sub i32 %i2, 1106 107 %cmp = icmp eq i32 %i3, 0108 br i1 %cmp, label %ret, label %loop109 110ret:111 ret half %x112}113