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1# RUN: llc -run-pass=si-insert-waitcnts -mtriple=amdgcn -mcpu=tahiti -o - %s | FileCheck %s -check-prefixes=CHECK,SI2# RUN: llc -run-pass=si-insert-waitcnts -mtriple=amdgcn -mcpu=gfx900 -o - %s | FileCheck %s -check-prefixes=CHECK,GFX93# RUN: llc -run-pass=si-insert-waitcnts -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -o - %s | FileCheck %s4# RUN: llc -run-pass=si-insert-waitcnts -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -o - %s | FileCheck %s5 6# RUN: llc -passes=si-insert-waitcnts -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -o - %s | FileCheck %s7---8# CHECK-LABEL: name: vccz_corrupt_workaround9# CHECK: $vcc = V_CMP_EQ_F3210# SI-NEXT: S_WAITCNT 12711# SI-NEXT: $vcc = S_MOV_B64 $vcc12# CHECK-NEXT: S_CBRANCH_VCCZ %bb.2, implicit killed $vcc13 14name: vccz_corrupt_workaround15tracksRegLiveness: true16body: |17 bb.0:18 liveins: $sgpr0_sgpr119 20 $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 11, 021 $sgpr7 = S_MOV_B32 6144022 $sgpr6 = S_MOV_B32 -123 $vcc = V_CMP_EQ_F32_e64 0, 0, 0, undef $sgpr2, 0, implicit $mode, implicit $exec24 S_CBRANCH_VCCZ %bb.1, implicit killed $vcc25 26 bb.2:27 liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x0000000328 29 $vgpr0 = V_MOV_B32_e32 9, implicit $exec30 BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec31 $vgpr0 = V_MOV_B32_e32 0, implicit $exec32 S_BRANCH %bb.333 34 bb.1:35 liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x0000000336 37 $vgpr0 = V_MOV_B32_e32 100, implicit $exec38 BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec39 $vgpr0 = V_MOV_B32_e32 1, implicit $exec40 41 bb.3:42 liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3:0x0000000343 44 $sgpr3 = S_MOV_B32 6144045 $sgpr2 = S_MOV_B32 -146 BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec47 S_ENDPGM 048 49...50---51# CHECK-LABEL: name: vccz_corrupt_undef_vcc52# CHECK: BUFFER_STORE_DWORD_OFFSET53# SI-NEXT: S_WAITCNT 385554# CHECK-NEXT: $vgpr0 = V_MOV_B32_e3255 56name: vccz_corrupt_undef_vcc57tracksRegLiveness: true58body: |59 bb.0:60 liveins: $sgpr0_sgpr161 62 $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 11, 063 $sgpr7 = S_MOV_B32 6144064 $sgpr6 = S_MOV_B32 -165 S_CBRANCH_VCCZ %bb.1, implicit undef $vcc66 67 bb.2:68 liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x0000000369 70 $vgpr0 = V_MOV_B32_e32 9, implicit $exec71 BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec72 $vgpr0 = V_MOV_B32_e32 0, implicit $exec73 S_BRANCH %bb.374 75 bb.1:76 liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x0000000377 78 $vgpr0 = V_MOV_B32_e32 100, implicit $exec79 BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec80 $vgpr0 = V_MOV_B32_e32 1, implicit $exec81 82 bb.3:83 liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3:0x0000000384 85 $sgpr3 = S_MOV_B32 6144086 $sgpr2 = S_MOV_B32 -187 BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec88 S_ENDPGM 089 90...91---92# Test that after reloading vcc spilled to a vgpr, we insert any necessary93# instructions to fix vccz.94 95# CHECK-LABEL: name: reload_vcc_from_vgpr96# CHECK: $vcc_lo = V_READLANE_B32 $vgpr0, 8, implicit-def $vcc97# CHECK: $vcc_hi = V_READLANE_B32 $vgpr0, 998# SI: $vcc = S_MOV_B64 $vcc99# GFX9: $vcc = S_MOV_B64 $vcc100# CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc101 102name: reload_vcc_from_vgpr103body: |104 bb.0:105 $vcc_lo = V_READLANE_B32 $vgpr0, 8, implicit-def $vcc106 $vcc_hi = V_READLANE_B32 $vgpr0, 9107 S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc108 bb.1:109 110...111---112# Test that after reloading vcc spilled to memory, we insert any necessary113# instructions to fix vccz.114 115# CHECK-LABEL: name: reload_vcc_from_mem116# CHECK: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, implicit $exec117# CHECK: $vcc_lo = V_READFIRSTLANE_B32 killed $vgpr0, implicit $exec, implicit-def $vcc118# CHECK: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 8, 0, 0, implicit $exec119# CHECK: $vcc_hi = V_READFIRSTLANE_B32 killed $vgpr0, implicit $exec, implicit-def $vcc120# SI: $vcc = S_MOV_B64 $vcc121# GFX9: $vcc = S_MOV_B64 $vcc122# CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc123 124name: reload_vcc_from_mem125body: |126 bb.0:127 $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, implicit $exec128 $vcc_lo = V_READFIRSTLANE_B32 killed $vgpr0, implicit $exec, implicit-def $vcc129 $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 8, 0, 0, implicit $exec130 $vcc_hi = V_READFIRSTLANE_B32 killed $vgpr0, implicit $exec, implicit-def $vcc131 S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc132 bb.1:133 134...135---136# Test that after inline asm that defines vcc_lo, we insert any necessary137# instructions to fix vccz.138 139# CHECK-LABEL: name: inlineasm_def_vcc_lo140# CHECK: INLINEASM &"; def vcc_lo", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vcc_lo141# SI: $vcc = S_MOV_B64 $vcc142# GFX9: $vcc = S_MOV_B64 $vcc143# CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc144 145name: inlineasm_def_vcc_lo146body: |147 bb.0:148 INLINEASM &"; def vcc_lo", 1, 10, implicit-def $vcc_lo149 S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc150 bb.1:151 152...153---154# Test that after inline asm that defines vcc, no unnecessary instructions are155# inserted to fix vccz.156 157# CHECK-LABEL: name: inlineasm_def_vcc158# CHECK: INLINEASM &"; def vcc", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vcc159# CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc160 161name: inlineasm_def_vcc162body: |163 bb.0:164 INLINEASM &"; def vcc", 1, 10, implicit-def $vcc165 S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc166 bb.1:167 168...169---170# Test vcc definition in a previous basic block.171 172# CHECK-LABEL: name: vcc_def_pred173# CHECK: bb.1:174# SI: $vcc = S_MOV_B64 $vcc175# GFX9: $vcc = S_MOV_B64 $vcc176# CHECK: S_CBRANCH_VCCZ %bb.2, implicit $vcc177 178name: vcc_def_pred179body: |180 bb.0:181 $vcc = S_MOV_B64 0182 bb.1:183 S_CBRANCH_VCCZ %bb.2, implicit $vcc184 bb.2:185 186...187 188# Test various ways that the live range of vccz can overlap with the live range189# of an outstanding smem load.190 191---192# CHECK-LABEL: name: load_wait_def_use193# SI: S_WAITCNT 0194# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0195# SI-NEXT: S_WAITCNT 127196# SI-NEXT: $vcc = S_MOV_B64 0197# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc198name: load_wait_def_use199body: |200 bb.0:201 $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0202 S_WAITCNT 127203 $vcc = S_MOV_B64 0204 S_CBRANCH_VCCZ %bb.1, implicit $vcc205 bb.1:206...207 208---209# CHECK-LABEL: name: load_wait_nop_def_use210# SI: S_WAITCNT 0211# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0212# SI-NEXT: S_WAITCNT 127213# SI-NEXT: S_NOP 0214# SI-NEXT: $vcc = S_MOV_B64 0215# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc216name: load_wait_nop_def_use217body: |218 bb.0:219 $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0220 S_WAITCNT 127221 S_NOP 0222 $vcc = S_MOV_B64 0223 S_CBRANCH_VCCZ %bb.1, implicit $vcc224 bb.1:225...226 227---228# CHECK-LABEL: name: load_def_wait_use229# SI: S_WAITCNT 0230# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0231# SI-NEXT: $vcc = S_MOV_B64 0232# SI-NEXT: S_WAITCNT 127233# SI-NEXT: $vcc = S_MOV_B64 $vcc234# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc235name: load_def_wait_use236body: |237 bb.0:238 $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0239 $vcc = S_MOV_B64 0240 S_WAITCNT 127241 S_CBRANCH_VCCZ %bb.1, implicit $vcc242 bb.1:243...244 245# CHECK-LABEL: name: load_def_wait_nop_use246# SI: S_WAITCNT 0247# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0248# SI-NEXT: $vcc = S_MOV_B64 0249# SI-NEXT: S_WAITCNT 127250# SI-NEXT: S_NOP 0251# SI-NEXT: $vcc = S_MOV_B64 $vcc252# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc253name: load_def_wait_nop_use254body: |255 bb.0:256 $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0257 $vcc = S_MOV_B64 0258 S_WAITCNT 127259 S_NOP 0260 S_CBRANCH_VCCZ %bb.1, implicit $vcc261 bb.1:262...263 264---265# CHECK-LABEL: name: load_def_use266# SI: S_WAITCNT 0267# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0268# SI-NEXT: $vcc = S_MOV_B64 0269# SI-NEXT: S_WAITCNT 127270# SI-NEXT: $vcc = S_MOV_B64 $vcc271# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc272name: load_def_use273body: |274 bb.0:275 $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0276 $vcc = S_MOV_B64 0277 S_CBRANCH_VCCZ %bb.1, implicit $vcc278 bb.1:279...280 281---282# CHECK-LABEL: name: def_load_wait_use283# SI: S_WAITCNT 0284# SI-NEXT: $vcc = S_MOV_B64 0285# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0286# SI-NEXT: S_WAITCNT 127287# SI-NEXT: $vcc = S_MOV_B64 $vcc288# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc289name: def_load_wait_use290body: |291 bb.0:292 $vcc = S_MOV_B64 0293 $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0294 S_WAITCNT 127295 S_CBRANCH_VCCZ %bb.1, implicit $vcc296 bb.1:297...298 299---300# CHECK-LABEL: name: def_load_wait_nop_use301# SI: S_WAITCNT 0302# SI-NEXT: $vcc = S_MOV_B64 0303# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0304# SI-NEXT: S_WAITCNT 127305# SI-NEXT: S_NOP 0306# SI-NEXT: $vcc = S_MOV_B64 $vcc307# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc308name: def_load_wait_nop_use309body: |310 bb.0:311 $vcc = S_MOV_B64 0312 $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0313 S_WAITCNT 127314 S_NOP 0315 S_CBRANCH_VCCZ %bb.1, implicit $vcc316 bb.1:317...318 319---320# CHECK-LABEL: name: def_load_use321# SI: S_WAITCNT 0322# SI-NEXT: $vcc = S_MOV_B64 0323# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0324# SI-NEXT: S_WAITCNT 127325# SI-NEXT: $vcc = S_MOV_B64 $vcc326# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc327name: def_load_use328body: |329 bb.0:330 $vcc = S_MOV_B64 0331 $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0332 S_CBRANCH_VCCZ %bb.1, implicit $vcc333 bb.1:334...335