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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; Ensure that range metadata is handled correctly for vector loads.3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s4 5define <2 x i16> @test_add2x16(ptr %a_ptr, ptr %b_ptr) {6; CHECK-LABEL: test_add2x16:7; CHECK: ; %bb.0:8; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9; CHECK-NEXT: v_mov_b32_e32 v0, 0x30003010; CHECK-NEXT: s_setpc_b64 s[30:31]11 %a = load <2 x i16>, ptr %a_ptr, !range !0, !noundef !{}12 %b = load <2 x i16>, ptr %b_ptr, !range !1, !noundef !{}13 %result = add <2 x i16> %a, %b14 ret <2 x i16> %result15}16 17define <2 x i32> @test_add2x32(ptr %a_ptr, ptr %b_ptr) {18; CHECK-LABEL: test_add2x32:19; CHECK: ; %bb.0:20; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)21; CHECK-NEXT: flat_load_dwordx2 v[4:5], v[0:1]22; CHECK-NEXT: flat_load_dwordx2 v[6:7], v[2:3]23; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)24; CHECK-NEXT: v_or_b32_e32 v1, v5, v725; CHECK-NEXT: v_or_b32_e32 v0, v4, v626; CHECK-NEXT: s_setpc_b64 s[30:31]27 %a = load <2 x i32>, ptr %a_ptr, !range !2, !noundef !{}28 %b = load <2 x i32>, ptr %b_ptr, !range !3, !noundef !{}29 %result = add <2 x i32> %a, %b30 ret <2 x i32> %result31}32 33define <2 x i64> @test_add2x64(ptr %a_ptr, ptr %b_ptr) {34; CHECK-LABEL: test_add2x64:35; CHECK: ; %bb.0:36; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)37; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[0:1]38; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)39; CHECK-NEXT: flat_load_dwordx4 v[6:9], v[2:3]40; CHECK-NEXT: ; kill: killed $vgpr0 killed $vgpr141; CHECK-NEXT: ; kill: killed $vgpr2 killed $vgpr342; CHECK-NEXT: v_mov_b32_e32 v2, 4843; CHECK-NEXT: v_mov_b32_e32 v3, 044; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)45; CHECK-NEXT: v_or_b32_e32 v1, v5, v746; CHECK-NEXT: v_or_b32_e32 v0, v4, v647; CHECK-NEXT: s_setpc_b64 s[30:31]48 %a = load <2 x i64>, ptr %a_ptr, !range !4, !noundef !{}49 %b = load <2 x i64>, ptr %b_ptr, !range !5, !noundef !{}50 %result = add <2 x i64> %a, %b51 ret <2 x i64> %result52}53 54define <3 x i16> @test_add3x16(ptr %a_ptr, ptr %b_ptr) {55; CHECK-LABEL: test_add3x16:56; CHECK: ; %bb.0:57; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)58; CHECK-NEXT: flat_load_dwordx2 v[4:5], v[0:1]59; CHECK-NEXT: flat_load_dwordx2 v[6:7], v[2:3]60; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)61; CHECK-NEXT: v_or_b32_e32 v1, v5, v762; CHECK-NEXT: v_or_b32_e32 v0, v4, v663; CHECK-NEXT: s_setpc_b64 s[30:31]64 %a = load <3 x i16>, ptr %a_ptr, !range !0, !noundef !{}65 %b = load <3 x i16>, ptr %b_ptr, !range !1, !noundef !{}66 %result = add <3 x i16> %a, %b67 ret <3 x i16> %result68}69 70define <3 x i32> @test_add3x32(ptr %a_ptr, ptr %b_ptr) {71; CHECK-LABEL: test_add3x32:72; CHECK: ; %bb.0:73; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)74; CHECK-NEXT: flat_load_dword v4, v[2:3]75; CHECK-NEXT: flat_load_dword v5, v[0:1]76; CHECK-NEXT: v_mov_b32_e32 v1, 4877; CHECK-NEXT: v_mov_b32_e32 v2, 4878; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)79; CHECK-NEXT: v_or_b32_e32 v0, v5, v480; CHECK-NEXT: s_setpc_b64 s[30:31]81 %a = load <3 x i32>, ptr %a_ptr, !range !2, !noundef !{}82 %b = load <3 x i32>, ptr %b_ptr, !range !3, !noundef !{}83 %result = add <3 x i32> %a, %b84 ret <3 x i32> %result85}86 87define <3 x i64> @test_add3x64(ptr %a_ptr, ptr %b_ptr) {88; CHECK-LABEL: test_add3x64:89; CHECK: ; %bb.0:90; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)91; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[0:1]92; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)93; CHECK-NEXT: flat_load_dwordx4 v[6:9], v[2:3]94; CHECK-NEXT: ; kill: killed $vgpr0 killed $vgpr195; CHECK-NEXT: ; kill: killed $vgpr2 killed $vgpr396; CHECK-NEXT: v_mov_b32_e32 v2, 4897; CHECK-NEXT: v_mov_b32_e32 v3, 098; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)99; CHECK-NEXT: v_or_b32_e32 v1, v5, v7100; CHECK-NEXT: v_or_b32_e32 v0, v4, v6101; CHECK-NEXT: v_mov_b32_e32 v4, 48102; CHECK-NEXT: v_mov_b32_e32 v5, 0103; CHECK-NEXT: s_setpc_b64 s[30:31]104 %a = load <3 x i64>, ptr %a_ptr, !range !4, !noundef !{}105 %b = load <3 x i64>, ptr %b_ptr, !range !5, !noundef !{}106 %result = add <3 x i64> %a, %b107 ret <3 x i64> %result108}109 110!0 = !{i16 16, i16 17 }111!1 = !{i16 32, i16 33 }112!2 = !{i32 16, i32 17 }113!3 = !{i32 32, i32 33 }114!4 = !{i64 16, i64 17 }115!5 = !{i64 32, i64 33 }116