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1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s2 3; GCN-LABEL: {{^}}load_idx_idy:4; GCN-NOT: global_load5; GCN: s_load_dword [[ID_XY:s[0-9]+]], s[4:5], 0x46; GCN-NOT: global_load7; GCN: s_lshr_b32 [[ID_Y:s[0-9]+]], [[ID_XY]], 168; GCN: s_add_i32 [[ID_SUM:s[0-9]+]], [[ID_Y]], [[ID_XY]]9; GCN: s_and_b32 s{{[0-9]+}}, [[ID_SUM]], 0xffff10define protected amdgpu_kernel void @load_idx_idy(ptr addrspace(1) %out) {11entry:12 %disp = tail call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()13 %gep_x = getelementptr i8, ptr addrspace(4) %disp, i64 414 %id_x = load i16, ptr addrspace(4) %gep_x, align 4, !invariant.load !0 ; load workgroup size x15 %gep_y = getelementptr i8, ptr addrspace(4) %disp, i64 616 %id_y = load i16, ptr addrspace(4) %gep_y, align 2, !invariant.load !0 ; load workgroup size y17 %add = add nuw nsw i16 %id_y, %id_x18 %conv = zext i16 %add to i3219 store i32 %conv, ptr addrspace(1) %out, align 420 ret void21}22 23; A little more complicated case where more sub-dword loads could be coalesced24; if they are not widening earlier.25; GCN-LABEL: {{^}}load_4i16:26; GCN: s_load_dwordx2 s[[[D0:[0-9]+]]:[[D1:[0-9]+]]], s[4:5], 0x427; GCN-NOT: s_load_dword {{s[0-9]+}}, s[4:5], 0x428; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s[[D0]], 1629; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s[[D1]], 1630; GCN: s_endpgm31define protected amdgpu_kernel void @load_4i16(ptr addrspace(1) %out) {32entry:33 %disp = tail call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()34 %gep_x = getelementptr i8, ptr addrspace(4) %disp, i64 435 %id_x = load i16, ptr addrspace(4) %gep_x, align 4, !invariant.load !0 ; load workgroup size x36 %gep_y = getelementptr i8, ptr addrspace(4) %disp, i64 637 %id_y = load i16, ptr addrspace(4) %gep_y, align 2, !invariant.load !0 ; load workgroup size y38 %gep_z = getelementptr i8, ptr addrspace(4) %disp, i64 839 %id_z = load i16, ptr addrspace(4) %gep_z, align 4, !invariant.load !0 ; load workgroup size x40 %gep_w = getelementptr i8, ptr addrspace(4) %disp, i64 1041 %id_w = load i16, ptr addrspace(4) %gep_w, align 2, !invariant.load !0 ; load workgroup size y42 %add = add nuw nsw i16 %id_y, %id_x43 %add2 = add nuw nsw i16 %id_z, %id_w44 %add3 = add nuw nsw i16 %add, %add245 %conv = zext i16 %add3 to i3246 store i32 %conv, ptr addrspace(1) %out, align 447 ret void48}49 50declare ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()51 52!0 = !{!0}53