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1# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=machineverifier -filetype=null %s 2>&1 | FileCheck %s2# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx90a --passes='machine-function(verify)' -filetype=null %s 2>&1 | FileCheck %s3 4# Implicit uses are OK.5---6name: implicit_use7body: |8 bb.0:9 $vgpr1_vgpr2 = IMPLICIT_DEF10 S_NOP 0, implicit $vgpr1_vgpr211 %0:vreg_64 = IMPLICIT_DEF12 S_NOP 0, implicit %013 14 %1:sreg_64_xexec = IMPLICIT_DEF15 %2:sreg_64_xexec = SI_CALL %1, 0, csr_amdgpu, implicit $vgpr1_vgpr216 17 ; noreg is OK18 DS_WRITE_B64_gfx9 $noreg, $noreg, 0, 0, implicit $exec19...20 21# The unaligned registers are allowed to exist, just not on any tuple instructions.22 23---24name: copy_like_generic25body: |26 bb.0:27 $vgpr1_vgpr2 = IMPLICIT_DEF28 $vgpr3_vgpr4 = COPY $vgpr1_vgpr229 %0:vreg_64 = IMPLICIT_DEF30 %1:vreg_64 = COPY %031...32 33---34name: mov_32_unaligned_super35body: |36 bb.0:37 undef %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec38 %1:vgpr_32 = V_MOV_B32_e32 undef %2.sub1:vreg_64, implicit $exec39...40 41# Well-aligned subregister indexes are OK42---43name: aligned_sub_reg44body: |45 bb.0:46 %0:vreg_64_align2 = IMPLICIT_DEF47 %1:vreg_128_align2 = IMPLICIT_DEF48 GLOBAL_STORE_DWORDX2 %0, %1.sub0_sub1, 0, 0, implicit $exec49 GLOBAL_STORE_DWORDX2 %0, %1.sub2_sub3, 0, 0, implicit $exec50...51 52---53name: unaligned_registers54body: |55 bb.0:56 liveins: $vgpr0_vgpr1, $vgpr3_vgpr4_vgpr5_vgpr657 %0:vreg_64_align2 = IMPLICIT_DEF58 %1:vreg_64 = IMPLICIT_DEF59 %2:vreg_96 = IMPLICIT_DEF60 %3:vreg_128 = IMPLICIT_DEF61 %4:areg_64 = IMPLICIT_DEF62 %5:vreg_128_align2 = IMPLICIT_DEF63 64 ; Check virtual register uses65 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***66 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***67 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***68 GLOBAL_STORE_DWORDX2 %0, %1, 0, 0, implicit $exec69 GLOBAL_STORE_DWORDX3 %0, %2, 0, 0, implicit $exec70 GLOBAL_STORE_DWORDX4 %0, %3, 0, 0, implicit $exec71 72 ; Check virtual registers with subregisters73 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***74 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***75 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***76 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***77 GLOBAL_STORE_DWORDX2 %0, %3.sub0_sub1, 0, 0, implicit $exec78 GLOBAL_STORE_DWORDX2 %0, %3.sub2_sub3, 0, 0, implicit $exec79 GLOBAL_STORE_DWORDX2 %0, %3.sub1_sub2, 0, 0, implicit $exec80 GLOBAL_STORE_DWORDX2 %0, %5.sub1_sub2, 0, 0, implicit $exec81 82 ; Check physical register uses83 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***84 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***85 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***86 GLOBAL_STORE_DWORDX2 $vgpr0_vgpr1, $vgpr3_vgpr4, 0, 0, implicit $exec87 GLOBAL_STORE_DWORDX3 $vgpr0_vgpr1, $vgpr3_vgpr4_vgpr5, 0, 0, implicit $exec88 GLOBAL_STORE_DWORDX4 $vgpr0_vgpr1, $vgpr3_vgpr4_vgpr5_vgpr6, 0, 0, implicit $exec89 90 ; Check virtual register defs91 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***92 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***93 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***94 %6:vreg_64 = GLOBAL_LOAD_DWORDX2 %0, 0, 0, implicit $exec95 %7:vreg_96 = GLOBAL_LOAD_DWORDX3 %0, 0, 0, implicit $exec96 %8:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec97 98 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***99 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***100 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***101 $vgpr1_vgpr2 = GLOBAL_LOAD_DWORDX2 %0, 0, 0, implicit $exec102 $vgpr1_vgpr2_vgpr3 = GLOBAL_LOAD_DWORDX3 %0, 0, 0, implicit $exec103 $vgpr1_vgpr2_vgpr3_vgpr4 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec104 105 ; Check AGPRs106 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***107 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***108 %9:vgpr_32 = IMPLICIT_DEF109 %10:areg_64 = IMPLICIT_DEF110 %11:areg_128_align2 = IMPLICIT_DEF111 DS_WRITE_B64_gfx9 %9, %10, 0, 0, implicit $exec112 DS_WRITE_B64_gfx9 %9, %11.sub1_sub2, 0, 0, implicit $exec113 114 ; Check aligned vgprs for FP32 Packed Math instructions.115 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***116 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***117 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***118 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***119 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***120 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***121 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***122 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***123 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***124 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***125 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***126 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***127 %12:vreg_64 = IMPLICIT_DEF128 %13:vreg_64_align2 = IMPLICIT_DEF129 %14:areg_96_align2 = IMPLICIT_DEF130 $vgpr3_vgpr4 = V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec131 $vgpr0_vgpr1 = V_PK_ADD_F32 0, %12, 11, %13, 0, 0, 0, 0, implicit $mode, implicit $exec132 $vgpr0_vgpr1 = V_PK_ADD_F32 0, %13, 11, %12, 0, 0, 0, 0, 0, implicit $mode, implicit $exec133 $vgpr0_vgpr1 = V_PK_ADD_F32 0, %13, 11, %14.sub1_sub2, 0, 0, 0, 0, 0, implicit $mode, implicit $exec134 $vgpr0_vgpr1 = V_PK_ADD_F32 0, %14.sub1_sub2, 11, %13, 0, 0, 0, 0, implicit $mode, implicit $exec135 $vgpr0_vgpr1 = V_PK_MUL_F32 0, %12, 11, %13, 0, 0, 0, 0, implicit $mode, implicit $exec136 $vgpr0_vgpr1 = V_PK_MUL_F32 0, %13, 11, %12, 0, 0, 0, 0, 0, implicit $mode, implicit $exec137 $vgpr0_vgpr1 = V_PK_MUL_F32 0, %13, 11, %14.sub1_sub2, 0, 0, 0, 0, 0, implicit $mode, implicit $exec138 $vgpr0_vgpr1 = V_PK_MUL_F32 0, %14.sub1_sub2, 11, %13, 0, 0, 0, 0, implicit $mode, implicit $exec139 $vgpr0_vgpr1 = nofpexcept V_PK_FMA_F32 8, %12, 8, %13, 11, %14.sub0_sub1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec140 $vgpr0_vgpr1 = nofpexcept V_PK_FMA_F32 8, %13, 8, %12, 11, %14.sub0_sub1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec141 $vgpr0_vgpr1 = nofpexcept V_PK_FMA_F32 8, %13, 8, %13, 11, %14.sub1_sub2, 0, 0, 0, 0, 0, implicit $mode, implicit $exec142...143 144# FIXME: Inline asm is not verified145# ; Check inline asm146# ; XCHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***147# ; XCHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***148# ; XCHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***149# INLINEASM &"; use $0 ", 1 /* sideeffect attdialect */, 9 /* reguse */, $vgpr1_vgpr2150# INLINEASM &"; use $0 ", 1 /* sideeffect attdialect */, 9 /* reguse */, %4151# INLINEASM &"; use $0 ", 1 /* sideeffect attdialect */, 9 /* reguse */, %5.sub1_sub2152