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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -amdgpu-opt-vgpr-liverange=true -stop-after=si-opt-vgpr-liverange < %s | FileCheck -check-prefix=SI %s3 4; a normal if-else5define amdgpu_ps float @else1(i32 %z, float %v) #0 {6 ; SI-LABEL: name: else17 ; SI: bb.0.main_body:8 ; SI-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)9 ; SI-NEXT: liveins: $vgpr0, $vgpr110 ; SI-NEXT: {{ $}}11 ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr112 ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr013 ; SI-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 6, killed [[COPY1]], implicit $exec14 ; SI-NEXT: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF killed [[V_CMP_GT_I32_e64_]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec15 ; SI-NEXT: S_BRANCH %bb.316 ; SI-NEXT: {{ $}}17 ; SI-NEXT: bb.1.Flow:18 ; SI-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)19 ; SI-NEXT: {{ $}}20 ; SI-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %9:vgpr_32, %bb.0, %4, %bb.321 ; SI-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, undef %14:vgpr_32, %bb.322 ; SI-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32 = SI_ELSE killed [[SI_IF]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec23 ; SI-NEXT: S_BRANCH %bb.224 ; SI-NEXT: {{ $}}25 ; SI-NEXT: bb.2.if:26 ; SI-NEXT: successors: %bb.4(0x80000000)27 ; SI-NEXT: {{ $}}28 ; SI-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, killed [[PHI1]], 0, [[PHI1]], 0, 0, implicit $mode, implicit $exec29 ; SI-NEXT: S_BRANCH %bb.430 ; SI-NEXT: {{ $}}31 ; SI-NEXT: bb.3.else:32 ; SI-NEXT: successors: %bb.1(0x80000000)33 ; SI-NEXT: {{ $}}34 ; SI-NEXT: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MUL_F32_e64 0, 1077936128, 0, killed [[COPY]], 0, 0, implicit $mode, implicit $exec35 ; SI-NEXT: S_BRANCH %bb.136 ; SI-NEXT: {{ $}}37 ; SI-NEXT: bb.4.end:38 ; SI-NEXT: [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[PHI]], %bb.1, [[V_ADD_F32_e64_]], %bb.239 ; SI-NEXT: SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec40 ; SI-NEXT: $vgpr0 = COPY killed [[PHI2]]41 ; SI-NEXT: SI_RETURN_TO_EPILOG killed $vgpr042main_body:43 %cc = icmp sgt i32 %z, 544 br i1 %cc, label %if, label %else45 46if:47 %v.if = fmul float %v, 2.048 br label %end49 50else:51 %v.else = fmul float %v, 3.052 br label %end53 54end:55 %r = phi float [ %v.if, %if ], [ %v.else, %else ]56 ret float %r57}58 59 60; %v was used after if-else61define amdgpu_ps float @else2(i32 %z, float %v) #0 {62 ; SI-LABEL: name: else263 ; SI: bb.0.main_body:64 ; SI-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)65 ; SI-NEXT: liveins: $vgpr0, $vgpr166 ; SI-NEXT: {{ $}}67 ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr168 ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr069 ; SI-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 6, killed [[COPY1]], implicit $exec70 ; SI-NEXT: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF killed [[V_CMP_GT_I32_e64_]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec71 ; SI-NEXT: S_BRANCH %bb.372 ; SI-NEXT: {{ $}}73 ; SI-NEXT: bb.1.Flow:74 ; SI-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)75 ; SI-NEXT: {{ $}}76 ; SI-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %10:vgpr_32, %bb.0, %4, %bb.377 ; SI-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32 = SI_ELSE killed [[SI_IF]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec78 ; SI-NEXT: S_BRANCH %bb.279 ; SI-NEXT: {{ $}}80 ; SI-NEXT: bb.2.if:81 ; SI-NEXT: successors: %bb.4(0x80000000)82 ; SI-NEXT: {{ $}}83 ; SI-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, killed [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec84 ; SI-NEXT: S_BRANCH %bb.485 ; SI-NEXT: {{ $}}86 ; SI-NEXT: bb.3.else:87 ; SI-NEXT: successors: %bb.1(0x80000000)88 ; SI-NEXT: {{ $}}89 ; SI-NEXT: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MUL_F32_e64 0, 1077936128, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec90 ; SI-NEXT: S_BRANCH %bb.191 ; SI-NEXT: {{ $}}92 ; SI-NEXT: bb.4.end:93 ; SI-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.1, [[V_ADD_F32_e64_]], %bb.294 ; SI-NEXT: [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[PHI]], %bb.1, [[V_ADD_F32_e64_]], %bb.295 ; SI-NEXT: SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec96 ; SI-NEXT: [[V_ADD_F32_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, killed [[PHI1]], 0, killed [[PHI2]], 0, 0, implicit $mode, implicit $exec97 ; SI-NEXT: $vgpr0 = COPY killed [[V_ADD_F32_e64_1]]98 ; SI-NEXT: SI_RETURN_TO_EPILOG killed $vgpr099main_body:100 %cc = icmp sgt i32 %z, 5101 br i1 %cc, label %if, label %else102 103if:104 %v.if = fmul float %v, 2.0105 br label %end106 107else:108 %v.else = fmul float %v, 3.0109 br label %end110 111end:112 %r0 = phi float [ %v.if, %if ], [ %v, %else ]113 %r1 = phi float [ %v.if, %if ], [ %v.else, %else ]114 %r2 = fadd float %r0, %r1115 ret float %r2116}117 118; if-else inside loop, %x can be optimized, but %v cannot be.119define amdgpu_ps float @else3(i32 %z, float %v, i32 inreg %bound, i32 %x0) #0 {120 ; SI-LABEL: name: else3121 ; SI: bb.0.entry:122 ; SI-NEXT: successors: %bb.1(0x80000000)123 ; SI-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0, $vgpr2124 ; SI-NEXT: {{ $}}125 ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr2126 ; SI-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY killed $sgpr0127 ; SI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1128 ; SI-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0129 ; SI-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 6, killed [[COPY3]], implicit $exec130 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0131 ; SI-NEXT: {{ $}}132 ; SI-NEXT: bb.1.for.body:133 ; SI-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)134 ; SI-NEXT: {{ $}}135 ; SI-NEXT: [[PHI:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_]], %bb.0, %14, %bb.5136 ; SI-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %13, %bb.5137 ; SI-NEXT: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[V_CMP_GT_I32_e64_]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec138 ; SI-NEXT: S_BRANCH %bb.4139 ; SI-NEXT: {{ $}}140 ; SI-NEXT: bb.2.Flow:141 ; SI-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)142 ; SI-NEXT: {{ $}}143 ; SI-NEXT: [[PHI2:%[0-9]+]]:vgpr_32 = PHI undef %25:vgpr_32, %bb.1, %10, %bb.4144 ; SI-NEXT: [[PHI3:%[0-9]+]]:vgpr_32 = PHI undef %26:vgpr_32, %bb.1, %9, %bb.4145 ; SI-NEXT: [[PHI4:%[0-9]+]]:vgpr_32 = PHI [[PHI1]], %bb.1, undef %32:vgpr_32, %bb.4146 ; SI-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32 = SI_ELSE killed [[SI_IF]], %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec147 ; SI-NEXT: S_BRANCH %bb.3148 ; SI-NEXT: {{ $}}149 ; SI-NEXT: bb.3.if:150 ; SI-NEXT: successors: %bb.5(0x80000000)151 ; SI-NEXT: {{ $}}152 ; SI-NEXT: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MUL_F32_e64 0, [[PHI]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec153 ; SI-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 1, killed [[PHI4]], 0, implicit $exec154 ; SI-NEXT: S_BRANCH %bb.5155 ; SI-NEXT: {{ $}}156 ; SI-NEXT: bb.4.else:157 ; SI-NEXT: successors: %bb.2(0x80000000)158 ; SI-NEXT: {{ $}}159 ; SI-NEXT: [[V_MUL_F32_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_MUL_F32_e64 0, [[COPY2]], 0, [[PHI1]], 0, 0, implicit $mode, implicit $exec160 ; SI-NEXT: [[V_LSHL_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_LSHL_ADD_U32_e64 killed [[PHI1]], 1, [[PHI1]], implicit $exec161 ; SI-NEXT: S_BRANCH %bb.2162 ; SI-NEXT: {{ $}}163 ; SI-NEXT: bb.5.if.end:164 ; SI-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000)165 ; SI-NEXT: {{ $}}166 ; SI-NEXT: [[PHI5:%[0-9]+]]:vgpr_32 = PHI [[PHI3]], %bb.2, [[V_MUL_F32_e64_]], %bb.3167 ; SI-NEXT: [[PHI6:%[0-9]+]]:vgpr_32 = PHI [[PHI2]], %bb.2, [[V_ADD_U32_e64_]], %bb.3168 ; SI-NEXT: SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec169 ; SI-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 1, [[PHI6]], 0, implicit $exec170 ; SI-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 killed [[PHI]], 1, implicit-def dead $scc171 ; SI-NEXT: S_CMP_LT_I32 [[S_ADD_I32_]], [[COPY1]], implicit-def $scc172 ; SI-NEXT: S_CBRANCH_SCC1 %bb.1, implicit killed $scc173 ; SI-NEXT: S_BRANCH %bb.6174 ; SI-NEXT: {{ $}}175 ; SI-NEXT: bb.6.for.end:176 ; SI-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, killed [[PHI6]], 0, killed [[PHI5]], 0, 0, implicit $mode, implicit $exec177 ; SI-NEXT: $vgpr0 = COPY killed [[V_ADD_F32_e64_]]178 ; SI-NEXT: SI_RETURN_TO_EPILOG killed $vgpr0179entry:180 br label %for.body181 182for.body:183 %i = phi i32 [ 0, %entry ], [ %inc, %if.end ]184 %x = phi i32 [ %x0, %entry ], [ %xinc, %if.end ]185 %cc = icmp sgt i32 %z, 5186 br i1 %cc, label %if, label %else187 188if:189 %i.tmp = bitcast i32 %i to float190 %v.if = fmul float %v, %i.tmp191 %x.if = add i32 %x, 1192 br label %if.end193 194else:195 %x.tmp = bitcast i32 %x to float196 %v.else = fmul float %v, %x.tmp197 %x.else = mul i32 %x, 3198 br label %if.end199 200if.end:201 %v.endif = phi float [ %v.if, %if ], [ %v.else, %else ]202 %x.endif = phi i32 [ %x.if, %if ], [ %x.else, %else ]203 204 %xinc = add i32 %x.endif, 1205 %inc = add i32 %i, 1206 %cond = icmp slt i32 %inc, %bound207 br i1 %cond, label %for.body, label %for.end208 209for.end:210 %x_float = bitcast i32 %x.endif to float211 %r = fadd float %x_float, %v.endif212 ret float %r213}214 215; a loop inside an if-else216define amdgpu_ps float @loop(i32 %z, float %v, i32 inreg %bound, ptr %extern_func, ptr %extern_func2) #0 {217 ; SI-LABEL: name: loop218 ; SI: bb.0.main_body:219 ; SI-NEXT: successors: %bb.6(0x40000000), %bb.1(0x40000000)220 ; SI-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5221 ; SI-NEXT: {{ $}}222 ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr5223 ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr4224 ; SI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY killed $vgpr3225 ; SI-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed $vgpr2226 ; SI-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1227 ; SI-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0228 ; SI-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 6, killed [[COPY5]], implicit $exec229 ; SI-NEXT: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF killed [[V_CMP_GT_I32_e64_]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec230 ; SI-NEXT: S_BRANCH %bb.6231 ; SI-NEXT: {{ $}}232 ; SI-NEXT: bb.1.Flow:233 ; SI-NEXT: successors: %bb.2(0x40000000), %bb.10(0x40000000)234 ; SI-NEXT: {{ $}}235 ; SI-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %16:vgpr_32, %bb.0, %4, %bb.9236 ; SI-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY4]], %bb.0, undef %48:vgpr_32, %bb.9237 ; SI-NEXT: [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[COPY3]], %bb.0, undef %50:vgpr_32, %bb.9238 ; SI-NEXT: [[PHI3:%[0-9]+]]:vgpr_32 = PHI [[COPY2]], %bb.0, undef %52:vgpr_32, %bb.9239 ; SI-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32 = SI_ELSE killed [[SI_IF]], %bb.10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec240 ; SI-NEXT: S_BRANCH %bb.2241 ; SI-NEXT: {{ $}}242 ; SI-NEXT: bb.2.if:243 ; SI-NEXT: successors: %bb.3(0x80000000)244 ; SI-NEXT: {{ $}}245 ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[PHI2]], %subreg.sub0, killed [[PHI3]], %subreg.sub1246 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo247 ; SI-NEXT: [[COPY6:%[0-9]+]]:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103248 ; SI-NEXT: {{ $}}249 ; SI-NEXT: bb.3:250 ; SI-NEXT: successors: %bb.4(0x80000000)251 ; SI-NEXT: {{ $}}252 ; SI-NEXT: [[PHI4:%[0-9]+]]:vreg_64 = PHI undef %54:vreg_64, %bb.4, [[REG_SEQUENCE]], %bb.2253 ; SI-NEXT: [[PHI5:%[0-9]+]]:vgpr_32 = PHI undef %56:vgpr_32, %bb.4, [[PHI1]], %bb.2254 ; SI-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI4]].sub0, implicit $exec255 ; SI-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI4]].sub1, implicit $exec256 ; SI-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_1]], %subreg.sub1257 ; SI-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], killed [[PHI4]], implicit $exec258 ; SI-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[V_CMP_EQ_U64_e64_]], implicit-def $exec, implicit-def dead $scc, implicit $exec259 ; SI-NEXT: {{ $}}260 ; SI-NEXT: bb.4:261 ; SI-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)262 ; SI-NEXT: {{ $}}263 ; SI-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32264 ; SI-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY6]]265 ; SI-NEXT: $vgpr0 = COPY killed [[PHI5]]266 ; SI-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed [[REG_SEQUENCE1]], 0, csr_amdgpu_si_gfx, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $vgpr0, implicit-def $vgpr0267 ; SI-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32268 ; SI-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0269 ; SI-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, killed [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc270 ; SI-NEXT: SI_WATERFALL_LOOP %bb.3, implicit $exec271 ; SI-NEXT: {{ $}}272 ; SI-NEXT: bb.5:273 ; SI-NEXT: successors: %bb.10(0x80000000)274 ; SI-NEXT: {{ $}}275 ; SI-NEXT: $exec_lo = S_MOV_B32 killed [[S_MOV_B32_]]276 ; SI-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY killed [[COPY7]]277 ; SI-NEXT: S_BRANCH %bb.10278 ; SI-NEXT: {{ $}}279 ; SI-NEXT: bb.6.else:280 ; SI-NEXT: successors: %bb.7(0x80000000)281 ; SI-NEXT: {{ $}}282 ; SI-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[COPY1]], %subreg.sub0, killed [[COPY]], %subreg.sub1283 ; SI-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo284 ; SI-NEXT: [[COPY9:%[0-9]+]]:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103285 ; SI-NEXT: {{ $}}286 ; SI-NEXT: bb.7:287 ; SI-NEXT: successors: %bb.8(0x80000000)288 ; SI-NEXT: {{ $}}289 ; SI-NEXT: [[PHI6:%[0-9]+]]:vreg_64 = PHI undef %58:vreg_64, %bb.8, [[REG_SEQUENCE2]], %bb.6290 ; SI-NEXT: [[PHI7:%[0-9]+]]:vgpr_32 = PHI undef %60:vgpr_32, %bb.8, [[COPY4]], %bb.6291 ; SI-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI6]].sub0, implicit $exec292 ; SI-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI6]].sub1, implicit $exec293 ; SI-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_2]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_3]], %subreg.sub1294 ; SI-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE3]], killed [[PHI6]], implicit $exec295 ; SI-NEXT: [[S_AND_SAVEEXEC_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[V_CMP_EQ_U64_e64_1]], implicit-def $exec, implicit-def dead $scc, implicit $exec296 ; SI-NEXT: {{ $}}297 ; SI-NEXT: bb.8:298 ; SI-NEXT: successors: %bb.7(0x40000000), %bb.9(0x40000000)299 ; SI-NEXT: {{ $}}300 ; SI-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32301 ; SI-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY9]]302 ; SI-NEXT: $vgpr0 = COPY killed [[PHI7]]303 ; SI-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed [[REG_SEQUENCE3]], 0, csr_amdgpu_si_gfx, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $vgpr0, implicit-def $vgpr0304 ; SI-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32305 ; SI-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0306 ; SI-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, killed [[S_AND_SAVEEXEC_B32_1]], implicit-def dead $scc307 ; SI-NEXT: SI_WATERFALL_LOOP %bb.7, implicit $exec308 ; SI-NEXT: {{ $}}309 ; SI-NEXT: bb.9:310 ; SI-NEXT: successors: %bb.1(0x80000000)311 ; SI-NEXT: {{ $}}312 ; SI-NEXT: $exec_lo = S_MOV_B32 killed [[S_MOV_B32_1]]313 ; SI-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY killed [[COPY10]]314 ; SI-NEXT: S_BRANCH %bb.1315 ; SI-NEXT: {{ $}}316 ; SI-NEXT: bb.10.end:317 ; SI-NEXT: [[PHI8:%[0-9]+]]:vgpr_32 = PHI [[PHI]], %bb.1, [[COPY8]], %bb.5318 ; SI-NEXT: SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec319 ; SI-NEXT: $vgpr0 = COPY killed [[PHI8]]320 ; SI-NEXT: SI_RETURN_TO_EPILOG killed $vgpr0321main_body:322 %cc = icmp sgt i32 %z, 5323 br i1 %cc, label %if, label %else324 325if:326 %v.if = call amdgpu_gfx float %extern_func(float %v)327 br label %end328 329else:330 %v.else = call amdgpu_gfx float %extern_func2(float %v)331 br label %end332 333end:334 %r = phi float [ %v.if, %if ], [ %v.else, %else ]335 ret float %r336}337 338; a loop inside an if-else, but the variable is still in use after the if-else339define amdgpu_ps float @loop_with_use(i32 %z, float %v, i32 inreg %bound, ptr %extern_func, ptr %extern_func2) #0 {340 ; SI-LABEL: name: loop_with_use341 ; SI: bb.0.main_body:342 ; SI-NEXT: successors: %bb.6(0x40000000), %bb.1(0x40000000)343 ; SI-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5344 ; SI-NEXT: {{ $}}345 ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr5346 ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr4347 ; SI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY killed $vgpr3348 ; SI-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed $vgpr2349 ; SI-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1350 ; SI-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0351 ; SI-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 6, killed [[COPY5]], implicit $exec352 ; SI-NEXT: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF killed [[V_CMP_GT_I32_e64_]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec353 ; SI-NEXT: S_BRANCH %bb.6354 ; SI-NEXT: {{ $}}355 ; SI-NEXT: bb.1.Flow:356 ; SI-NEXT: successors: %bb.2(0x40000000), %bb.10(0x40000000)357 ; SI-NEXT: {{ $}}358 ; SI-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %16:vgpr_32, %bb.0, %4, %bb.9359 ; SI-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY3]], %bb.0, undef %49:vgpr_32, %bb.9360 ; SI-NEXT: [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[COPY2]], %bb.0, undef %51:vgpr_32, %bb.9361 ; SI-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32 = SI_ELSE killed [[SI_IF]], %bb.10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec362 ; SI-NEXT: S_BRANCH %bb.2363 ; SI-NEXT: {{ $}}364 ; SI-NEXT: bb.2.if:365 ; SI-NEXT: successors: %bb.3(0x80000000)366 ; SI-NEXT: {{ $}}367 ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[PHI1]], %subreg.sub0, killed [[PHI2]], %subreg.sub1368 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo369 ; SI-NEXT: [[COPY6:%[0-9]+]]:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103370 ; SI-NEXT: {{ $}}371 ; SI-NEXT: bb.3:372 ; SI-NEXT: successors: %bb.4(0x80000000)373 ; SI-NEXT: {{ $}}374 ; SI-NEXT: [[PHI3:%[0-9]+]]:vreg_64 = PHI undef %53:vreg_64, %bb.4, [[REG_SEQUENCE]], %bb.2375 ; SI-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI3]].sub0, implicit $exec376 ; SI-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI3]].sub1, implicit $exec377 ; SI-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_1]], %subreg.sub1378 ; SI-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], killed [[PHI3]], implicit $exec379 ; SI-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[V_CMP_EQ_U64_e64_]], implicit-def $exec, implicit-def dead $scc, implicit $exec380 ; SI-NEXT: {{ $}}381 ; SI-NEXT: bb.4:382 ; SI-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)383 ; SI-NEXT: {{ $}}384 ; SI-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32385 ; SI-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY6]]386 ; SI-NEXT: $vgpr0 = COPY [[COPY4]]387 ; SI-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed [[REG_SEQUENCE1]], 0, csr_amdgpu_si_gfx, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $vgpr0, implicit-def $vgpr0388 ; SI-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32389 ; SI-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0390 ; SI-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, killed [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc391 ; SI-NEXT: SI_WATERFALL_LOOP %bb.3, implicit $exec392 ; SI-NEXT: {{ $}}393 ; SI-NEXT: bb.5:394 ; SI-NEXT: successors: %bb.10(0x80000000)395 ; SI-NEXT: {{ $}}396 ; SI-NEXT: $exec_lo = S_MOV_B32 killed [[S_MOV_B32_]]397 ; SI-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY killed [[COPY7]]398 ; SI-NEXT: S_BRANCH %bb.10399 ; SI-NEXT: {{ $}}400 ; SI-NEXT: bb.6.else:401 ; SI-NEXT: successors: %bb.7(0x80000000)402 ; SI-NEXT: {{ $}}403 ; SI-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[COPY1]], %subreg.sub0, killed [[COPY]], %subreg.sub1404 ; SI-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo405 ; SI-NEXT: [[COPY9:%[0-9]+]]:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103406 ; SI-NEXT: {{ $}}407 ; SI-NEXT: bb.7:408 ; SI-NEXT: successors: %bb.8(0x80000000)409 ; SI-NEXT: {{ $}}410 ; SI-NEXT: [[PHI4:%[0-9]+]]:vreg_64 = PHI undef %55:vreg_64, %bb.8, [[REG_SEQUENCE2]], %bb.6411 ; SI-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI4]].sub0, implicit $exec412 ; SI-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI4]].sub1, implicit $exec413 ; SI-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_2]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_3]], %subreg.sub1414 ; SI-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE3]], killed [[PHI4]], implicit $exec415 ; SI-NEXT: [[S_AND_SAVEEXEC_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[V_CMP_EQ_U64_e64_1]], implicit-def $exec, implicit-def dead $scc, implicit $exec416 ; SI-NEXT: {{ $}}417 ; SI-NEXT: bb.8:418 ; SI-NEXT: successors: %bb.7(0x40000000), %bb.9(0x40000000)419 ; SI-NEXT: {{ $}}420 ; SI-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32421 ; SI-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY9]]422 ; SI-NEXT: $vgpr0 = COPY [[COPY4]]423 ; SI-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed [[REG_SEQUENCE3]], 0, csr_amdgpu_si_gfx, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $vgpr0, implicit-def $vgpr0424 ; SI-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32425 ; SI-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0426 ; SI-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, killed [[S_AND_SAVEEXEC_B32_1]], implicit-def dead $scc427 ; SI-NEXT: SI_WATERFALL_LOOP %bb.7, implicit $exec428 ; SI-NEXT: {{ $}}429 ; SI-NEXT: bb.9:430 ; SI-NEXT: successors: %bb.1(0x80000000)431 ; SI-NEXT: {{ $}}432 ; SI-NEXT: $exec_lo = S_MOV_B32 killed [[S_MOV_B32_1]]433 ; SI-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY killed [[COPY10]]434 ; SI-NEXT: S_BRANCH %bb.1435 ; SI-NEXT: {{ $}}436 ; SI-NEXT: bb.10.end:437 ; SI-NEXT: [[PHI5:%[0-9]+]]:vgpr_32 = PHI [[PHI]], %bb.1, [[COPY8]], %bb.5438 ; SI-NEXT: SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec439 ; SI-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, killed [[PHI5]], 0, killed [[COPY4]], 0, 0, implicit $mode, implicit $exec440 ; SI-NEXT: $vgpr0 = COPY killed [[V_ADD_F32_e64_]]441 ; SI-NEXT: SI_RETURN_TO_EPILOG killed $vgpr0442main_body:443 %cc = icmp sgt i32 %z, 5444 br i1 %cc, label %if, label %else445 446if:447 %v.if = call amdgpu_gfx float %extern_func(float %v)448 br label %end449 450else:451 %v.else = call amdgpu_gfx float %extern_func2(float %v)452 br label %end453 454end:455 %r = phi float [ %v.if, %if ], [ %v.else, %else ]456 %r2 = fadd float %r, %v457 ret float %r2458}459 460define amdgpu_kernel void @livevariables_update_missed_block(ptr addrspace(1) %src1) {461 ; SI-LABEL: name: livevariables_update_missed_block462 ; SI: bb.0.entry:463 ; SI-NEXT: successors: %bb.2(0x40000000), %bb.5(0x40000000)464 ; SI-NEXT: liveins: $vgpr0, $sgpr4_sgpr5465 ; SI-NEXT: {{ $}}466 ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY killed $sgpr4_sgpr5467 ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY killed $vgpr0468 ; SI-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY1]](s32), implicit $exec469 ; SI-NEXT: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF killed [[V_CMP_NE_U32_e64_]], %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec470 ; SI-NEXT: S_BRANCH %bb.2471 ; SI-NEXT: {{ $}}472 ; SI-NEXT: bb.1.if.then:473 ; SI-NEXT: successors: %bb.7(0x80000000)474 ; SI-NEXT: {{ $}}475 ; SI-NEXT: early-clobber %34:sreg_64_xexec = S_LOAD_DWORDX2_IMM_ec killed [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.src1.kernarg.offset, align 4, addrspace 4)476 ; SI-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %34.sub0, killed %52, 0, implicit $exec477 ; SI-NEXT: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADDC_U32_e64 0, killed %34.sub1, killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec478 ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[V_ADD_CO_U32_e64_]], %subreg.sub0, killed [[V_ADDC_U32_e64_]], %subreg.sub1479 ; SI-NEXT: [[GLOBAL_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_UBYTE killed [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load (s8) from %ir.i10, addrspace 1)480 ; SI-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 0, implicit $exec481 ; SI-NEXT: GLOBAL_STORE_BYTE killed [[V_MOV_B]], killed [[GLOBAL_LOAD_UBYTE]], 0, 0, implicit $exec :: (store (s8) into `ptr addrspace(1) null`, addrspace 1)482 ; SI-NEXT: S_BRANCH %bb.7483 ; SI-NEXT: {{ $}}484 ; SI-NEXT: bb.2.if.then9:485 ; SI-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)486 ; SI-NEXT: {{ $}}487 ; SI-NEXT: S_CBRANCH_SCC0 %bb.4, implicit undef $scc488 ; SI-NEXT: {{ $}}489 ; SI-NEXT: bb.3:490 ; SI-NEXT: successors: %bb.6(0x80000000)491 ; SI-NEXT: {{ $}}492 ; SI-NEXT: S_BRANCH %bb.6493 ; SI-NEXT: {{ $}}494 ; SI-NEXT: bb.4.sw.bb:495 ; SI-NEXT: successors: %bb.6(0x80000000)496 ; SI-NEXT: {{ $}}497 ; SI-NEXT: [[V_MOV_B1:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 0, implicit $exec498 ; SI-NEXT: [[GLOBAL_LOAD_UBYTE1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_UBYTE killed [[V_MOV_B1]], 0, 0, implicit $exec :: ("amdgpu-noclobber" load (s8) from `ptr addrspace(1) null`, addrspace 1)499 ; SI-NEXT: S_BRANCH %bb.6500 ; SI-NEXT: {{ $}}501 ; SI-NEXT: bb.5.Flow:502 ; SI-NEXT: successors: %bb.1(0x40000000), %bb.7(0x40000000)503 ; SI-NEXT: {{ $}}504 ; SI-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY1]](s32), %bb.0, undef %53:vgpr_32, %bb.6505 ; SI-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32 = SI_ELSE killed [[SI_IF]], %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec506 ; SI-NEXT: S_BRANCH %bb.1507 ; SI-NEXT: {{ $}}508 ; SI-NEXT: bb.6.sw.bb18:509 ; SI-NEXT: successors: %bb.5(0x80000000)510 ; SI-NEXT: {{ $}}511 ; SI-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI undef %41:vgpr_32, %bb.3, [[GLOBAL_LOAD_UBYTE1]], %bb.4512 ; SI-NEXT: [[V_MOV_B2:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 0, implicit $exec513 ; SI-NEXT: GLOBAL_STORE_BYTE killed [[V_MOV_B2]], killed [[PHI1]], 0, 0, implicit $exec :: (store (s8) into `ptr addrspace(1) null`, addrspace 1)514 ; SI-NEXT: S_BRANCH %bb.5515 ; SI-NEXT: {{ $}}516 ; SI-NEXT: bb.7.UnifiedReturnBlock:517 ; SI-NEXT: SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec518 ; SI-NEXT: S_ENDPGM 0519entry:520 %i2 = tail call i32 @llvm.amdgcn.workitem.id.x()521 %i4 = add i32 0, %i2522 %i5 = zext i32 %i4 to i64523 %i6 = add i64 0, %i5524 %add = add i64 %i6, 0525 %cmp2 = icmp ult i64 %add, 1526 br i1 %cmp2, label %if.then, label %if.then9527 528if.then: ; preds = %entry529 %i9 = mul i64 %i6, 1530 %i10 = getelementptr inbounds i8, ptr addrspace(1) %src1, i64 %i9531 %i11 = load i8, ptr addrspace(1) %i10, align 1532 %i12 = insertelement <3 x i8> zeroinitializer, i8 %i11, i64 0533 %i13 = insertelement <3 x i8> %i12, i8 0, i64 1534 %i14 = insertelement <3 x i8> %i13, i8 0, i64 1535 %i15 = select <3 x i1> zeroinitializer, <3 x i8> zeroinitializer, <3 x i8> %i14536 %i16 = extractelement <3 x i8> %i15, i64 0537 store i8 %i16, ptr addrspace(1) null, align 1538 ret void539 540if.then9: ; preds = %entry541 %undef = freeze i1 poison542 br i1 %undef, label %sw.bb18, label %sw.bb543 544sw.bb: ; preds = %if.then9545 %i17 = load i8, ptr addrspace(1) null, align 1546 %i18 = insertelement <4 x i8> zeroinitializer, i8 %i17, i64 0547 %a.sroa.0.0.vecblend = shufflevector <4 x i8> %i18, <4 x i8> zeroinitializer, <4 x i32> <i32 0, i32 0, i32 0, i32 poison>548 br label %sw.bb18549 550sw.bb18: ; preds = %sw.bb, %if.then9551 %a.sroa.0.0 = phi <4 x i8> [ %a.sroa.0.0.vecblend, %sw.bb ], [ poison, %if.then9 ]552 %a.sroa.0.0.vec.extract61 = shufflevector <4 x i8> %a.sroa.0.0, <4 x i8> zeroinitializer, <3 x i32> <i32 poison, i32 1, i32 poison>553 %i19 = insertelement <3 x i8> %a.sroa.0.0.vec.extract61, i8 0, i64 0554 %i20 = select <3 x i1> zeroinitializer, <3 x i8> zeroinitializer, <3 x i8> %i19555 %i21 = extractelement <3 x i8> %i20, i64 1556 store i8 %i21, ptr addrspace(1) null, align 1557 ret void558}559 560%tex = type opaque561define protected amdgpu_kernel void @nested_waterfalls(ptr addrspace(1) %tex.coerce) local_unnamed_addr {562 ; SI-LABEL: name: nested_waterfalls563 ; SI: bb.0.entry:564 ; SI-NEXT: successors: %bb.1(0x80000000)565 ; SI-NEXT: liveins: $vgpr0, $sgpr4_sgpr5566 ; SI-NEXT: {{ $}}567 ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY killed $sgpr4_sgpr5568 ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY killed $vgpr0569 ; SI-NEXT: {{ $}}570 ; SI-NEXT: bb.1.if.then:571 ; SI-NEXT: successors: %bb.2(0x80000000)572 ; SI-NEXT: {{ $}}573 ; SI-NEXT: early-clobber %11:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM_ec killed [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.tex.coerce.kernarg.offset, align 4, addrspace 4)574 ; SI-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = nuw nsw V_LSHLREV_B32_e64 3, killed [[COPY1]](s32), implicit $exec575 ; SI-NEXT: [[GLOBAL_LOAD_DWORDX2_SADDR:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2_SADDR killed %11, killed [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (s64) from %ir.idx, addrspace 1)576 ; SI-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 [[GLOBAL_LOAD_DWORDX2_SADDR]], 16, 0, implicit $exec :: (invariant load (s128) from %ir.3 + 16, addrspace 4)577 ; SI-NEXT: [[GLOBAL_LOAD_DWORDX4_1:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 [[GLOBAL_LOAD_DWORDX2_SADDR]], 0, 0, implicit $exec :: (invariant load (s128) from %ir.3, align 32, addrspace 4)578 ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_256 = REG_SEQUENCE killed [[GLOBAL_LOAD_DWORDX4_1]].sub0, %subreg.sub0, [[GLOBAL_LOAD_DWORDX4_1]].sub1, %subreg.sub1, [[GLOBAL_LOAD_DWORDX4_1]].sub2, %subreg.sub2, [[GLOBAL_LOAD_DWORDX4_1]].sub3, %subreg.sub3, killed [[GLOBAL_LOAD_DWORDX4_]].sub0, %subreg.sub4, [[GLOBAL_LOAD_DWORDX4_]].sub1, %subreg.sub5, [[GLOBAL_LOAD_DWORDX4_]].sub2, %subreg.sub6, [[GLOBAL_LOAD_DWORDX4_]].sub3, %subreg.sub7579 ; SI-NEXT: [[GLOBAL_LOAD_DWORDX4_2:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 killed [[GLOBAL_LOAD_DWORDX2_SADDR]], 48, 0, implicit $exec :: (invariant load (s128) from %ir.add.ptr.i, addrspace 4)580 ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo581 ; SI-NEXT: {{ $}}582 ; SI-NEXT: bb.2:583 ; SI-NEXT: successors: %bb.3(0x80000000)584 ; SI-NEXT: {{ $}}585 ; SI-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub0, implicit $exec586 ; SI-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub1, implicit $exec587 ; SI-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1588 ; SI-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 killed [[REG_SEQUENCE1]], [[REG_SEQUENCE]].sub0_sub1, implicit $exec589 ; SI-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub2, implicit $exec590 ; SI-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub3, implicit $exec591 ; SI-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1592 ; SI-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 killed [[REG_SEQUENCE2]], [[REG_SEQUENCE]].sub2_sub3, implicit $exec593 ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_EQ_U64_e64_]], killed [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc594 ; SI-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub4, implicit $exec595 ; SI-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub5, implicit $exec596 ; SI-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_4]], %subreg.sub0, [[V_READFIRSTLANE_B32_5]], %subreg.sub1597 ; SI-NEXT: [[V_CMP_EQ_U64_e64_2:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 killed [[REG_SEQUENCE3]], [[REG_SEQUENCE]].sub4_sub5, implicit $exec598 ; SI-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[S_AND_B32_]], killed [[V_CMP_EQ_U64_e64_2]], implicit-def dead $scc599 ; SI-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub6, implicit $exec600 ; SI-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[REG_SEQUENCE]].sub7, implicit $exec601 ; SI-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_6]], %subreg.sub0, [[V_READFIRSTLANE_B32_7]], %subreg.sub1602 ; SI-NEXT: [[V_CMP_EQ_U64_e64_3:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 killed [[REG_SEQUENCE4]], [[REG_SEQUENCE]].sub6_sub7, implicit $exec603 ; SI-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[S_AND_B32_1]], killed [[V_CMP_EQ_U64_e64_3]], implicit-def dead $scc604 ; SI-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_256 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_1]], %subreg.sub1, killed [[V_READFIRSTLANE_B32_2]], %subreg.sub2, killed [[V_READFIRSTLANE_B32_3]], %subreg.sub3, killed [[V_READFIRSTLANE_B32_4]], %subreg.sub4, killed [[V_READFIRSTLANE_B32_5]], %subreg.sub5, killed [[V_READFIRSTLANE_B32_6]], %subreg.sub6, killed [[V_READFIRSTLANE_B32_7]], %subreg.sub7605 ; SI-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[S_AND_B32_2]], implicit-def $exec, implicit-def dead $scc, implicit $exec606 ; SI-NEXT: {{ $}}607 ; SI-NEXT: bb.3:608 ; SI-NEXT: successors: %bb.4(0x80000000)609 ; SI-NEXT: {{ $}}610 ; SI-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo611 ; SI-NEXT: {{ $}}612 ; SI-NEXT: bb.4:613 ; SI-NEXT: successors: %bb.5(0x80000000)614 ; SI-NEXT: {{ $}}615 ; SI-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[GLOBAL_LOAD_DWORDX4_2]].sub0, implicit $exec616 ; SI-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[GLOBAL_LOAD_DWORDX4_2]].sub1, implicit $exec617 ; SI-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_8]], %subreg.sub0, [[V_READFIRSTLANE_B32_9]], %subreg.sub1618 ; SI-NEXT: [[V_CMP_EQ_U64_e64_4:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 killed [[REG_SEQUENCE6]], [[GLOBAL_LOAD_DWORDX4_2]].sub0_sub1, implicit $exec619 ; SI-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[GLOBAL_LOAD_DWORDX4_2]].sub2, implicit $exec620 ; SI-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[GLOBAL_LOAD_DWORDX4_2]].sub3, implicit $exec621 ; SI-NEXT: [[REG_SEQUENCE7:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_10]], %subreg.sub0, [[V_READFIRSTLANE_B32_11]], %subreg.sub1622 ; SI-NEXT: [[V_CMP_EQ_U64_e64_5:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 killed [[REG_SEQUENCE7]], [[GLOBAL_LOAD_DWORDX4_2]].sub2_sub3, implicit $exec623 ; SI-NEXT: [[S_AND_B32_3:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 killed [[V_CMP_EQ_U64_e64_4]], killed [[V_CMP_EQ_U64_e64_5]], implicit-def dead $scc624 ; SI-NEXT: [[REG_SEQUENCE8:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_8]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_9]], %subreg.sub1, killed [[V_READFIRSTLANE_B32_10]], %subreg.sub2, killed [[V_READFIRSTLANE_B32_11]], %subreg.sub3625 ; SI-NEXT: [[S_AND_SAVEEXEC_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[S_AND_B32_3]], implicit-def $exec, implicit-def dead $scc, implicit $exec626 ; SI-NEXT: {{ $}}627 ; SI-NEXT: bb.5:628 ; SI-NEXT: successors: %bb.4(0x40000000), %bb.6(0x40000000)629 ; SI-NEXT: {{ $}}630 ; SI-NEXT: [[IMAGE_SAMPLE_V1_V2_nsa_gfx10_:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_V1_V2_nsa_gfx10 undef %29:vgpr_32, undef %31:vgpr_32, [[REG_SEQUENCE5]], killed [[REG_SEQUENCE8]], 1, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8)631 ; SI-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, killed [[S_AND_SAVEEXEC_B32_1]], implicit-def dead $scc632 ; SI-NEXT: SI_WATERFALL_LOOP %bb.4, implicit $exec633 ; SI-NEXT: {{ $}}634 ; SI-NEXT: bb.6:635 ; SI-NEXT: successors: %bb.2(0x40000000), %bb.7(0x40000000)636 ; SI-NEXT: {{ $}}637 ; SI-NEXT: $exec_lo = S_MOV_B32 killed [[S_MOV_B32_1]]638 ; SI-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, killed [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc639 ; SI-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec640 ; SI-NEXT: {{ $}}641 ; SI-NEXT: bb.7:642 ; SI-NEXT: $exec_lo = S_MOV_B32 killed [[S_MOV_B32_]]643 ; SI-NEXT: GLOBAL_STORE_DWORD undef %35:vreg_64, killed [[IMAGE_SAMPLE_V1_V2_nsa_gfx10_]], 0, 0, implicit $exec :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)644 ; SI-NEXT: S_ENDPGM 0645entry:646 %0 = tail call i32 @llvm.amdgcn.workitem.id.x()647 %1 = zext i32 %0 to i64648 br label %if.then649 650if.then: ; preds = %entry651 %idx = getelementptr inbounds ptr, ptr addrspace(1) %tex.coerce, i64 %1652 %2 = load ptr, ptr addrspace(1) %idx, align 8653 %3 = addrspacecast ptr %2 to ptr addrspace(4)654 %add.ptr.i = getelementptr inbounds i32, ptr addrspace(4) %3, i64 12655 %4 = addrspacecast ptr %2 to ptr addrspace(4)656 %5 = load <8 x i32>, ptr addrspace(4) %4, align 32657 %6 = load <4 x i32>, ptr addrspace(4) %add.ptr.i, align 16658 %7 = tail call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float poison, float poison, <8 x i32> %5, <4 x i32> %6, i1 false, i32 0, i32 0)659 store float %7, ptr addrspace(1) poison, align 4660 ret void661}662 663declare i32 @llvm.amdgcn.workitem.id.x() #1664 665declare float @llvm.amdgcn.image.sample.2d.f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #2666 667attributes #0 = { nounwind }668attributes #1 = { nounwind readnone speculatable willreturn }669attributes #2 = { nounwind readonly willreturn }670