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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -amdgpu-opt-vgpr-liverange=true < %s | FileCheck -check-prefix=SI %s3 4; a normal if-else5define amdgpu_ps float @else1(i32 %z, float %v) #0 {6; SI-LABEL: else1:7; SI: ; %bb.0: ; %main_body8; SI-NEXT: v_cmp_gt_i32_e32 vcc_lo, 6, v09; SI-NEXT: ; implicit-def: $vgpr010; SI-NEXT: s_and_saveexec_b32 s0, vcc_lo11; SI-NEXT: s_xor_b32 s0, exec_lo, s012; SI-NEXT: s_cbranch_execnz .LBB0_313; SI-NEXT: ; %bb.1: ; %Flow14; SI-NEXT: s_andn2_saveexec_b32 s0, s015; SI-NEXT: s_cbranch_execnz .LBB0_416; SI-NEXT: .LBB0_2: ; %end17; SI-NEXT: s_or_b32 exec_lo, exec_lo, s018; SI-NEXT: s_branch .LBB0_519; SI-NEXT: .LBB0_3: ; %else20; SI-NEXT: v_mul_f32_e32 v0, 0x40400000, v121; SI-NEXT: ; implicit-def: $vgpr122; SI-NEXT: s_andn2_saveexec_b32 s0, s023; SI-NEXT: s_cbranch_execz .LBB0_224; SI-NEXT: .LBB0_4: ; %if25; SI-NEXT: v_add_f32_e32 v0, v1, v126; SI-NEXT: s_or_b32 exec_lo, exec_lo, s027; SI-NEXT: s_branch .LBB0_528; SI-NEXT: .LBB0_5:29main_body:30 %cc = icmp sgt i32 %z, 531 br i1 %cc, label %if, label %else32 33if:34 %v.if = fmul float %v, 2.035 br label %end36 37else:38 %v.else = fmul float %v, 3.039 br label %end40 41end:42 %r = phi float [ %v.if, %if ], [ %v.else, %else ]43 ret float %r44}45 46 47; %v was used after if-else48define amdgpu_ps float @else2(i32 %z, float %v) #0 {49; SI-LABEL: else2:50; SI: ; %bb.0: ; %main_body51; SI-NEXT: v_cmp_gt_i32_e32 vcc_lo, 6, v052; SI-NEXT: ; implicit-def: $vgpr053; SI-NEXT: s_and_saveexec_b32 s0, vcc_lo54; SI-NEXT: s_xor_b32 s0, exec_lo, s055; SI-NEXT: ; %bb.1: ; %else56; SI-NEXT: v_mul_f32_e32 v0, 0x40400000, v157; SI-NEXT: ; %bb.2: ; %Flow58; SI-NEXT: s_andn2_saveexec_b32 s0, s059; SI-NEXT: ; %bb.3: ; %if60; SI-NEXT: v_add_f32_e32 v1, v1, v161; SI-NEXT: v_mov_b32_e32 v0, v162; SI-NEXT: ; %bb.4: ; %end63; SI-NEXT: s_or_b32 exec_lo, exec_lo, s064; SI-NEXT: v_add_f32_e32 v0, v1, v065; SI-NEXT: ; return to shader part epilog66main_body:67 %cc = icmp sgt i32 %z, 568 br i1 %cc, label %if, label %else69 70if:71 %v.if = fmul float %v, 2.072 br label %end73 74else:75 %v.else = fmul float %v, 3.076 br label %end77 78end:79 %r0 = phi float [ %v.if, %if ], [ %v, %else ]80 %r1 = phi float [ %v.if, %if ], [ %v.else, %else ]81 %r2 = fadd float %r0, %r182 ret float %r283}84 85; if-else inside loop, %x can be optimized, but %v cannot be.86define amdgpu_ps float @else3(i32 %z, float %v, i32 inreg %bound, i32 %x0) #0 {87; SI-LABEL: else3:88; SI: ; %bb.0: ; %entry89; SI-NEXT: s_mov_b32 s1, 090; SI-NEXT: v_cmp_gt_i32_e32 vcc_lo, 6, v091; SI-NEXT: s_branch .LBB2_292; SI-NEXT: .LBB2_1: ; %if.end93; SI-NEXT: ; in Loop: Header=BB2_2 Depth=194; SI-NEXT: s_or_b32 exec_lo, exec_lo, s295; SI-NEXT: v_add_nc_u32_e32 v2, 1, v396; SI-NEXT: s_add_i32 s1, s1, 197; SI-NEXT: s_cmp_lt_i32 s1, s098; SI-NEXT: s_cbranch_scc0 .LBB2_699; SI-NEXT: .LBB2_2: ; %for.body100; SI-NEXT: ; =>This Inner Loop Header: Depth=1101; SI-NEXT: ; implicit-def: $vgpr3102; SI-NEXT: ; implicit-def: $vgpr0103; SI-NEXT: s_and_saveexec_b32 s2, vcc_lo104; SI-NEXT: s_xor_b32 s2, exec_lo, s2105; SI-NEXT: ; %bb.3: ; %else106; SI-NEXT: ; in Loop: Header=BB2_2 Depth=1107; SI-NEXT: v_mul_f32_e32 v0, v1, v2108; SI-NEXT: v_lshl_add_u32 v3, v2, 1, v2109; SI-NEXT: ; implicit-def: $vgpr2110; SI-NEXT: ; %bb.4: ; %Flow111; SI-NEXT: ; in Loop: Header=BB2_2 Depth=1112; SI-NEXT: s_andn2_saveexec_b32 s2, s2113; SI-NEXT: s_cbranch_execz .LBB2_1114; SI-NEXT: ; %bb.5: ; %if115; SI-NEXT: ; in Loop: Header=BB2_2 Depth=1116; SI-NEXT: v_mul_f32_e32 v0, s1, v1117; SI-NEXT: v_add_nc_u32_e32 v3, 1, v2118; SI-NEXT: s_branch .LBB2_1119; SI-NEXT: .LBB2_6: ; %for.end120; SI-NEXT: v_add_f32_e32 v0, v3, v0121; SI-NEXT: ; return to shader part epilog122entry:123; %break = icmp sgt i32 %bound, 0124; br i1 %break, label %for.body, label %for.end125 br label %for.body126 127for.body:128 %i = phi i32 [ 0, %entry ], [ %inc, %if.end ]129 %x = phi i32 [ %x0, %entry ], [ %xinc, %if.end ]130 %cc = icmp sgt i32 %z, 5131 br i1 %cc, label %if, label %else132 133if:134 %i.tmp = bitcast i32 %i to float135 %v.if = fmul float %v, %i.tmp136 %x.if = add i32 %x, 1137 br label %if.end138 139else:140 %x.tmp = bitcast i32 %x to float141 %v.else = fmul float %v, %x.tmp142 %x.else = mul i32 %x, 3143 br label %if.end144 145if.end:146 %v.endif = phi float [ %v.if, %if ], [ %v.else, %else ]147 %x.endif = phi i32 [ %x.if, %if ], [ %x.else, %else ]148 149 %xinc = add i32 %x.endif, 1150 %inc = add i32 %i, 1151 %cond = icmp slt i32 %inc, %bound152 br i1 %cond, label %for.body, label %for.end153 154for.end:155 %x_float = bitcast i32 %x.endif to float156 %r = fadd float %x_float, %v.endif157 ret float %r158}159 160; a loop inside an if-else161define amdgpu_ps float @loop(i32 %z, float %v, i32 inreg %bound, ptr %extern_func, ptr %extern_func2) #0 {162; SI-LABEL: loop:163; SI: ; %bb.0: ; %main_body164; SI-NEXT: v_mov_b32_e32 v6, v0165; SI-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0166; SI-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1167; SI-NEXT: s_mov_b32 s14, -1168; SI-NEXT: v_mov_b32_e32 v0, v1169; SI-NEXT: v_cmp_gt_i32_e32 vcc_lo, 6, v6170; SI-NEXT: s_mov_b32 s15, 0x31c16000171; SI-NEXT: s_add_u32 s12, s12, s1172; SI-NEXT: s_addc_u32 s13, s13, 0173; SI-NEXT: s_mov_b32 s32, 0174; SI-NEXT: ; implicit-def: $vgpr1175; SI-NEXT: s_and_saveexec_b32 s0, vcc_lo176; SI-NEXT: s_xor_b32 s6, exec_lo, s0177; SI-NEXT: s_cbranch_execz .LBB3_4178; SI-NEXT: ; %bb.1: ; %else179; SI-NEXT: s_mov_b32 s7, exec_lo180; SI-NEXT: .LBB3_2: ; =>This Inner Loop Header: Depth=1181; SI-NEXT: v_readfirstlane_b32 s4, v4182; SI-NEXT: v_readfirstlane_b32 s5, v5183; SI-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[4:5]184; SI-NEXT: s_and_saveexec_b32 s8, vcc_lo185; SI-NEXT: s_mov_b64 s[0:1], s[12:13]186; SI-NEXT: s_mov_b64 s[2:3], s[14:15]187; SI-NEXT: s_swappc_b64 s[30:31], s[4:5]188; SI-NEXT: v_mov_b32_e32 v1, v0189; SI-NEXT: ; implicit-def: $vgpr4_vgpr5190; SI-NEXT: ; implicit-def: $vgpr0191; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8192; SI-NEXT: s_cbranch_execnz .LBB3_2193; SI-NEXT: ; %bb.3:194; SI-NEXT: s_mov_b32 exec_lo, s7195; SI-NEXT: ; implicit-def: $vgpr0196; SI-NEXT: ; implicit-def: $vgpr2197; SI-NEXT: .LBB3_4: ; %Flow198; SI-NEXT: s_andn2_saveexec_b32 s6, s6199; SI-NEXT: s_cbranch_execz .LBB3_8200; SI-NEXT: ; %bb.5: ; %if201; SI-NEXT: s_mov_b32 s7, exec_lo202; SI-NEXT: .LBB3_6: ; =>This Inner Loop Header: Depth=1203; SI-NEXT: v_readfirstlane_b32 s4, v2204; SI-NEXT: v_readfirstlane_b32 s5, v3205; SI-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[2:3]206; SI-NEXT: s_and_saveexec_b32 s8, vcc_lo207; SI-NEXT: s_mov_b64 s[0:1], s[12:13]208; SI-NEXT: s_mov_b64 s[2:3], s[14:15]209; SI-NEXT: s_swappc_b64 s[30:31], s[4:5]210; SI-NEXT: v_mov_b32_e32 v1, v0211; SI-NEXT: ; implicit-def: $vgpr2_vgpr3212; SI-NEXT: ; implicit-def: $vgpr0213; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8214; SI-NEXT: s_cbranch_execnz .LBB3_6215; SI-NEXT: ; %bb.7:216; SI-NEXT: s_mov_b32 exec_lo, s7217; SI-NEXT: .LBB3_8: ; %end218; SI-NEXT: s_or_b32 exec_lo, exec_lo, s6219; SI-NEXT: v_mov_b32_e32 v0, v1220; SI-NEXT: ; return to shader part epilog221main_body:222 %cc = icmp sgt i32 %z, 5223 br i1 %cc, label %if, label %else224 225if:226 %v.if = call amdgpu_gfx float %extern_func(float %v)227 br label %end228 229else:230 %v.else = call amdgpu_gfx float %extern_func2(float %v)231 br label %end232 233end:234 %r = phi float [ %v.if, %if ], [ %v.else, %else ]235 ret float %r236}237 238; a loop inside an if-else, but the variable is still in use after the if-else239define amdgpu_ps float @loop_with_use(i32 %z, float %v, i32 inreg %bound, ptr %extern_func, ptr %extern_func2) #0 {240; SI-LABEL: loop_with_use:241; SI: ; %bb.0: ; %main_body242; SI-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0243; SI-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1244; SI-NEXT: s_mov_b32 s14, -1245; SI-NEXT: v_mov_b32_e32 v40, v1246; SI-NEXT: v_cmp_gt_i32_e32 vcc_lo, 6, v0247; SI-NEXT: s_mov_b32 s15, 0x31c16000248; SI-NEXT: s_add_u32 s12, s12, s1249; SI-NEXT: s_addc_u32 s13, s13, 0250; SI-NEXT: s_mov_b32 s32, 0251; SI-NEXT: ; implicit-def: $vgpr0252; SI-NEXT: s_and_saveexec_b32 s0, vcc_lo253; SI-NEXT: s_xor_b32 s6, exec_lo, s0254; SI-NEXT: s_cbranch_execz .LBB4_4255; SI-NEXT: ; %bb.1: ; %else256; SI-NEXT: s_mov_b32 s7, exec_lo257; SI-NEXT: .LBB4_2: ; =>This Inner Loop Header: Depth=1258; SI-NEXT: v_readfirstlane_b32 s4, v4259; SI-NEXT: v_readfirstlane_b32 s5, v5260; SI-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[4:5]261; SI-NEXT: s_and_saveexec_b32 s8, vcc_lo262; SI-NEXT: v_mov_b32_e32 v0, v40263; SI-NEXT: s_mov_b64 s[0:1], s[12:13]264; SI-NEXT: s_mov_b64 s[2:3], s[14:15]265; SI-NEXT: s_swappc_b64 s[30:31], s[4:5]266; SI-NEXT: ; implicit-def: $vgpr4_vgpr5267; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8268; SI-NEXT: s_cbranch_execnz .LBB4_2269; SI-NEXT: ; %bb.3:270; SI-NEXT: s_mov_b32 exec_lo, s7271; SI-NEXT: ; implicit-def: $vgpr2272; SI-NEXT: .LBB4_4: ; %Flow273; SI-NEXT: s_andn2_saveexec_b32 s6, s6274; SI-NEXT: s_cbranch_execz .LBB4_8275; SI-NEXT: ; %bb.5: ; %if276; SI-NEXT: s_mov_b32 s7, exec_lo277; SI-NEXT: .LBB4_6: ; =>This Inner Loop Header: Depth=1278; SI-NEXT: v_readfirstlane_b32 s4, v2279; SI-NEXT: v_readfirstlane_b32 s5, v3280; SI-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[2:3]281; SI-NEXT: s_and_saveexec_b32 s8, vcc_lo282; SI-NEXT: v_mov_b32_e32 v0, v40283; SI-NEXT: s_mov_b64 s[0:1], s[12:13]284; SI-NEXT: s_mov_b64 s[2:3], s[14:15]285; SI-NEXT: s_swappc_b64 s[30:31], s[4:5]286; SI-NEXT: ; implicit-def: $vgpr2_vgpr3287; SI-NEXT: s_xor_b32 exec_lo, exec_lo, s8288; SI-NEXT: s_cbranch_execnz .LBB4_6289; SI-NEXT: ; %bb.7:290; SI-NEXT: s_mov_b32 exec_lo, s7291; SI-NEXT: .LBB4_8: ; %end292; SI-NEXT: s_or_b32 exec_lo, exec_lo, s6293; SI-NEXT: v_add_f32_e32 v0, v0, v40294; SI-NEXT: ; return to shader part epilog295main_body:296 %cc = icmp sgt i32 %z, 5297 br i1 %cc, label %if, label %else298 299if:300 %v.if = call amdgpu_gfx float %extern_func(float %v)301 br label %end302 303else:304 %v.else = call amdgpu_gfx float %extern_func2(float %v)305 br label %end306 307end:308 %r = phi float [ %v.if, %if ], [ %v.else, %else ]309 %r2 = fadd float %r, %v310 ret float %r2311}312 313attributes #0 = { nounwind }314