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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 32# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -o - %s -run-pass=greedy -run-pass=amdgpu-mark-last-scratch-load -verify-machineinstrs | FileCheck -check-prefix=CHECK %s3# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -o - %s -passes=greedy,amdgpu-mark-last-scratch-load | FileCheck -check-prefix=CHECK %s4 5--- |6 define amdgpu_cs void @test_spill_12x32() "amdgpu-num-vgpr"="12" {7 ret void8 }9 define amdgpu_cs void @test_spill_384() "amdgpu-num-vgpr"="12" {10 ret void11 }12 define amdgpu_ps void @test_loop_12() "amdgpu-num-vgpr"="12" {13 ret void14 }15...16---17name: test_spill_12x3218tracksRegLiveness: true19machineFunctionInfo:20 stackPtrOffsetReg: '$sgpr32'21body: |22 bb.0:23 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr1124 25 ; CHECK-LABEL: name: test_spill_12x3226 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr1127 ; CHECK-NEXT: {{ $}}28 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr0, %stack.0, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)29 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr1, %stack.1, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5)30 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr2, %stack.2, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)31 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr3, %stack.3, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)32 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr4, %stack.4, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)33 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr5, %stack.5, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5)34 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr6, %stack.6, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5)35 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr7, %stack.7, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5)36 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr8, %stack.8, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5)37 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr9, %stack.9, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5)38 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr10, %stack.10, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5)39 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr11, %stack.11, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5)40 ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr1141 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.0, addrspace 5)42 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE1:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.1, addrspace 5)43 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE2:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.2, addrspace 5)44 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE3:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.3, $sgpr32, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.3, addrspace 5)45 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE4:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.4, $sgpr32, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.4, addrspace 5)46 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE5:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.5, $sgpr32, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.5, addrspace 5)47 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE6:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.6, $sgpr32, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.6, addrspace 5)48 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE7:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.7, $sgpr32, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.7, addrspace 5)49 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE8:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.8, $sgpr32, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.8, addrspace 5)50 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE9:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.9, $sgpr32, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.9, addrspace 5)51 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE10:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.10, $sgpr32, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.10, addrspace 5)52 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE11:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.11, $sgpr32, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.11, addrspace 5)53 ; CHECK-NEXT: S_ENDPGM 0, implicit [[SI_SPILL_V32_RESTORE]], implicit [[SI_SPILL_V32_RESTORE1]], implicit [[SI_SPILL_V32_RESTORE2]], implicit [[SI_SPILL_V32_RESTORE3]], implicit [[SI_SPILL_V32_RESTORE4]], implicit [[SI_SPILL_V32_RESTORE5]], implicit [[SI_SPILL_V32_RESTORE6]], implicit [[SI_SPILL_V32_RESTORE7]], implicit [[SI_SPILL_V32_RESTORE8]], implicit [[SI_SPILL_V32_RESTORE9]], implicit [[SI_SPILL_V32_RESTORE10]], implicit [[SI_SPILL_V32_RESTORE11]]54 %0:vgpr_32 = COPY $vgpr055 %1:vgpr_32 = COPY $vgpr156 %2:vgpr_32 = COPY $vgpr257 %3:vgpr_32 = COPY $vgpr358 %4:vgpr_32 = COPY $vgpr459 %5:vgpr_32 = COPY $vgpr560 %6:vgpr_32 = COPY $vgpr661 %7:vgpr_32 = COPY $vgpr762 %8:vgpr_32 = COPY $vgpr863 %9:vgpr_32 = COPY $vgpr964 %10:vgpr_32 = COPY $vgpr1065 %11:vgpr_32 = COPY $vgpr1166 INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr1167 S_ENDPGM 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7, implicit %8, implicit %9, implicit %10, implicit %1168...69 70---71name: test_spill_38472tracksRegLiveness: true73machineFunctionInfo:74 stackPtrOffsetReg: '$sgpr32'75body: |76 bb.0:77 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr1178 79 ; CHECK-LABEL: name: test_spill_38480 ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr1181 ; CHECK-NEXT: {{ $}}82 ; CHECK-NEXT: SI_SPILL_V384_SAVE $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11, %stack.0, $sgpr32, 0, implicit $exec :: (store (s384) into %stack.0, align 4, addrspace 5)83 ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr1184 ; CHECK-NEXT: [[SI_SPILL_V384_RESTORE:%[0-9]+]]:vreg_384 = SI_SPILL_V384_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: ("amdgpu-last-use" load (s384) from %stack.0, align 4, addrspace 5)85 ; CHECK-NEXT: S_ENDPGM 0, implicit [[SI_SPILL_V384_RESTORE]]86 %0:vreg_384 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr1187 INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr1188 S_ENDPGM 0, implicit %089...90 91---92name: test_loop_1293tracksRegLiveness: true94machineFunctionInfo:95 stackPtrOffsetReg: '$sgpr32'96body: |97 ; CHECK-LABEL: name: test_loop_1298 ; CHECK: bb.0:99 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)100 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12101 ; CHECK-NEXT: {{ $}}102 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr12, %stack.0, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)103 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr11, %stack.1, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5)104 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr10, %stack.2, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)105 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr9, %stack.3, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)106 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr8, %stack.4, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)107 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr7, %stack.5, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5)108 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr6, %stack.6, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5)109 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr5, %stack.7, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5)110 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr4, %stack.8, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5)111 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr3, %stack.9, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5)112 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr2, %stack.10, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5)113 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr1, %stack.11, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5)114 ; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr0, %stack.12, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5)115 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec116 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec117 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec118 ; CHECK-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec119 ; CHECK-NEXT: SI_SPILL_V32_SAVE [[V_MOV_B32_e32_3]], %stack.16, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5)120 ; CHECK-NEXT: %res5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec121 ; CHECK-NEXT: %res6:vgpr_32 = V_MOV_B32_e32 0, implicit $exec122 ; CHECK-NEXT: %res7:vgpr_32 = V_MOV_B32_e32 0, implicit $exec123 ; CHECK-NEXT: %res8:vgpr_32 = V_MOV_B32_e32 0, implicit $exec124 ; CHECK-NEXT: %res9:vgpr_32 = V_MOV_B32_e32 0, implicit $exec125 ; CHECK-NEXT: %res10:vgpr_32 = V_MOV_B32_e32 0, implicit $exec126 ; CHECK-NEXT: %res11:vgpr_32 = V_MOV_B32_e32 0, implicit $exec127 ; CHECK-NEXT: %res12:vgpr_32 = V_MOV_B32_e32 0, implicit $exec128 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.12, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.12, addrspace 5)129 ; CHECK-NEXT: %vcmp:sreg_32 = V_CMP_LT_I32_e64 0, [[SI_SPILL_V32_RESTORE]], implicit $exec130 ; CHECK-NEXT: %mask:sreg_32 = COPY $exec_lo, implicit-def $exec_lo131 ; CHECK-NEXT: %sand:sreg_32 = S_AND_B32 %mask, %vcmp, implicit-def dead $scc132 ; CHECK-NEXT: $exec_lo = S_MOV_B32_term %sand133 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec134 ; CHECK-NEXT: S_BRANCH %bb.1135 ; CHECK-NEXT: {{ $}}136 ; CHECK-NEXT: bb.1:137 ; CHECK-NEXT: successors: %bb.3(0x80000000)138 ; CHECK-NEXT: {{ $}}139 ; CHECK-NEXT: %mask2:sgpr_32 = S_MOV_B32 0140 ; CHECK-NEXT: %count:sgpr_32 = S_MOV_B32 0141 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec142 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec143 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec144 ; CHECK-NEXT: [[V_MOV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec145 ; CHECK-NEXT: %res5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec146 ; CHECK-NEXT: %res6:vgpr_32 = V_MOV_B32_e32 0, implicit $exec147 ; CHECK-NEXT: %res7:vgpr_32 = V_MOV_B32_e32 0, implicit $exec148 ; CHECK-NEXT: %res8:vgpr_32 = V_MOV_B32_e32 0, implicit $exec149 ; CHECK-NEXT: %res9:vgpr_32 = V_MOV_B32_e32 0, implicit $exec150 ; CHECK-NEXT: %res10:vgpr_32 = V_MOV_B32_e32 0, implicit $exec151 ; CHECK-NEXT: %res11:vgpr_32 = V_MOV_B32_e32 0, implicit $exec152 ; CHECK-NEXT: %res12:vgpr_32 = V_MOV_B32_e32 0, implicit $exec153 ; CHECK-NEXT: S_BRANCH %bb.3154 ; CHECK-NEXT: {{ $}}155 ; CHECK-NEXT: bb.2:156 ; CHECK-NEXT: successors: %bb.5(0x80000000)157 ; CHECK-NEXT: {{ $}}158 ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, %mask, implicit-def $scc159 ; CHECK-NEXT: S_BRANCH %bb.5160 ; CHECK-NEXT: {{ $}}161 ; CHECK-NEXT: bb.3:162 ; CHECK-NEXT: successors: %bb.4(0x04000000), %bb.3(0x7c000000)163 ; CHECK-NEXT: {{ $}}164 ; CHECK-NEXT: SI_SPILL_V32_SAVE [[V_MOV_B32_e32_1]], %stack.14, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5)165 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE1:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.11, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.11, addrspace 5)166 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[V_MOV_B32_e32_]], 0, [[SI_SPILL_V32_RESTORE1]], 0, 0, implicit $mode, implicit $exec167 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.14, $sgpr32, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.14, addrspace 5)168 ; CHECK-NEXT: SI_SPILL_V32_SAVE [[V_MOV_B32_e32_]], %stack.13, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5)169 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE2:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.10, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.10, addrspace 5)170 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[V_MOV_B32_e32_1]], 0, [[SI_SPILL_V32_RESTORE2]], 0, 0, implicit $mode, implicit $exec171 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE3:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.9, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5)172 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[V_MOV_B32_e32_2]], 0, [[SI_SPILL_V32_RESTORE3]], 0, 0, implicit $mode, implicit $exec173 ; CHECK-NEXT: SI_SPILL_V32_SAVE [[V_MOV_B32_e32_2]], %stack.15, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5)174 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE4:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.8, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.8, addrspace 5)175 ; CHECK-NEXT: [[V_MOV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[V_MOV_B32_e32_4]], 0, [[SI_SPILL_V32_RESTORE4]], 0, 0, implicit $mode, implicit $exec176 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE5:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.7, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.7, addrspace 5)177 ; CHECK-NEXT: %res5:vgpr_32 = V_ADD_F32_e64 0, %res5, 0, [[SI_SPILL_V32_RESTORE5]], 0, 0, implicit $mode, implicit $exec178 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE6:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.6, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5)179 ; CHECK-NEXT: %res6:vgpr_32 = V_ADD_F32_e64 0, %res6, 0, [[SI_SPILL_V32_RESTORE6]], 0, 0, implicit $mode, implicit $exec180 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE7:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.5, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5)181 ; CHECK-NEXT: %res7:vgpr_32 = V_ADD_F32_e64 0, %res7, 0, [[SI_SPILL_V32_RESTORE7]], 0, 0, implicit $mode, implicit $exec182 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE8:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.4, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5)183 ; CHECK-NEXT: %res8:vgpr_32 = V_ADD_F32_e64 0, %res8, 0, [[SI_SPILL_V32_RESTORE8]], 0, 0, implicit $mode, implicit $exec184 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE9:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.3, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5)185 ; CHECK-NEXT: %res9:vgpr_32 = V_ADD_F32_e64 0, %res9, 0, [[SI_SPILL_V32_RESTORE9]], 0, 0, implicit $mode, implicit $exec186 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE10:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5)187 ; CHECK-NEXT: %res10:vgpr_32 = V_ADD_F32_e64 0, %res10, 0, [[SI_SPILL_V32_RESTORE10]], 0, 0, implicit $mode, implicit $exec188 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE11:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5)189 ; CHECK-NEXT: %res11:vgpr_32 = V_ADD_F32_e64 0, %res11, 0, [[SI_SPILL_V32_RESTORE11]], 0, 0, implicit $mode, implicit $exec190 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE12:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5)191 ; CHECK-NEXT: %res12:vgpr_32 = V_ADD_F32_e64 0, %res12, 0, [[SI_SPILL_V32_RESTORE12]], 0, 0, implicit $mode, implicit $exec192 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.13, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.13, addrspace 5)193 ; CHECK-NEXT: %count:sgpr_32 = nuw nsw S_ADD_I32 %count, 1, implicit-def dead $scc194 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE13:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.12, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.12, addrspace 5)195 ; CHECK-NEXT: %vcmp2:sreg_32 = V_CMP_GE_I32_e64 %count, [[SI_SPILL_V32_RESTORE13]], implicit $exec196 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.15, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.15, addrspace 5)197 ; CHECK-NEXT: %mask2:sgpr_32 = S_OR_B32 %vcmp2, %mask2, implicit-def $scc198 ; CHECK-NEXT: $exec_lo = S_ANDN2_B32_term $exec_lo, %mask2, implicit-def $scc199 ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.3, implicit $exec200 ; CHECK-NEXT: S_BRANCH %bb.4201 ; CHECK-NEXT: {{ $}}202 ; CHECK-NEXT: bb.4:203 ; CHECK-NEXT: successors: %bb.2(0x80000000)204 ; CHECK-NEXT: {{ $}}205 ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, %mask2, implicit-def $scc206 ; CHECK-NEXT: SI_SPILL_V32_SAVE [[V_MOV_B32_e32_4]], %stack.16, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5)207 ; CHECK-NEXT: S_BRANCH %bb.2208 ; CHECK-NEXT: {{ $}}209 ; CHECK-NEXT: bb.5:210 ; CHECK-NEXT: [[SI_SPILL_V32_RESTORE14:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.16, $sgpr32, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.16, addrspace 5)211 ; CHECK-NEXT: EXP_DONE 0, [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_2]], [[SI_SPILL_V32_RESTORE14]], -1, 0, 15, implicit $exec212 ; CHECK-NEXT: EXP_DONE 0, %res5, %res6, %res7, %res8, -1, 0, 15, implicit $exec213 ; CHECK-NEXT: EXP_DONE 0, %res9, %res10, %res11, %res12, -1, 0, 15, implicit $exec214 ; CHECK-NEXT: S_ENDPGM 0215 bb.0: ; entry216 successors: %bb.1(0x40000000), %bb.2(0x40000000)217 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12218 219 %12:vgpr_32 = COPY $vgpr12220 %11:vgpr_32 = COPY $vgpr11221 %10:vgpr_32 = COPY $vgpr10222 %9:vgpr_32 = COPY $vgpr9223 %8:vgpr_32 = COPY $vgpr8224 %7:vgpr_32 = COPY $vgpr7225 %6:vgpr_32 = COPY $vgpr6226 %5:vgpr_32 = COPY $vgpr5227 %4:vgpr_32 = COPY $vgpr4228 %3:vgpr_32 = COPY $vgpr3229 %2:vgpr_32 = COPY $vgpr2230 %1:vgpr_32 = COPY $vgpr1231 %loop_end:vgpr_32 = COPY $vgpr0232 %res1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec233 %res2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec234 %res3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec235 %res4:vgpr_32 = V_MOV_B32_e32 0, implicit $exec236 %res5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec237 %res6:vgpr_32 = V_MOV_B32_e32 0, implicit $exec238 %res7:vgpr_32 = V_MOV_B32_e32 0, implicit $exec239 %res8:vgpr_32 = V_MOV_B32_e32 0, implicit $exec240 %res9:vgpr_32 = V_MOV_B32_e32 0, implicit $exec241 %res10:vgpr_32 = V_MOV_B32_e32 0, implicit $exec242 %res11:vgpr_32 = V_MOV_B32_e32 0, implicit $exec243 %res12:vgpr_32 = V_MOV_B32_e32 0, implicit $exec244 %vcmp:sreg_32 = V_CMP_LT_I32_e64 0, %loop_end, implicit $exec245 %mask:sreg_32 = COPY $exec_lo, implicit-def $exec_lo246 %sand:sreg_32 = S_AND_B32 %mask, %vcmp, implicit-def dead $scc247 $exec_lo = S_MOV_B32_term %sand248 S_CBRANCH_EXECZ %bb.2, implicit $exec249 S_BRANCH %bb.1250 251 bb.1: ; loop preheader252 successors: %bb.3(0x80000000)253 254 %mask2:sgpr_32 = S_MOV_B32 0255 %count:sgpr_32 = S_MOV_B32 0256 %res1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec257 %res2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec258 %res3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec259 %res4:vgpr_32 = V_MOV_B32_e32 0, implicit $exec260 %res5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec261 %res6:vgpr_32 = V_MOV_B32_e32 0, implicit $exec262 %res7:vgpr_32 = V_MOV_B32_e32 0, implicit $exec263 %res8:vgpr_32 = V_MOV_B32_e32 0, implicit $exec264 %res9:vgpr_32 = V_MOV_B32_e32 0, implicit $exec265 %res10:vgpr_32 = V_MOV_B32_e32 0, implicit $exec266 %res11:vgpr_32 = V_MOV_B32_e32 0, implicit $exec267 %res12:vgpr_32 = V_MOV_B32_e32 0, implicit $exec268 S_BRANCH %bb.3269 270 bb.2: ; flow271 successors: %bb.5(0x80000000)272 273 $exec_lo = S_OR_B32 $exec_lo, %mask, implicit-def $scc274 S_BRANCH %bb.5275 276 bb.3: ; loop277 successors: %bb.4(0x04000000), %bb.3(0x7c000000)278 279 %res1:vgpr_32 = V_ADD_F32_e64 0, %res1, 0, %1, 0, 0, implicit $mode, implicit $exec280 %res2:vgpr_32 = V_ADD_F32_e64 0, %res2, 0, %2, 0, 0, implicit $mode, implicit $exec281 %res3:vgpr_32 = V_ADD_F32_e64 0, %res3, 0, %3, 0, 0, implicit $mode, implicit $exec282 %res4:vgpr_32 = V_ADD_F32_e64 0, %res4, 0, %4, 0, 0, implicit $mode, implicit $exec283 %res5:vgpr_32 = V_ADD_F32_e64 0, %res5, 0, %5, 0, 0, implicit $mode, implicit $exec284 %res6:vgpr_32 = V_ADD_F32_e64 0, %res6, 0, %6, 0, 0, implicit $mode, implicit $exec285 %res7:vgpr_32 = V_ADD_F32_e64 0, %res7, 0, %7, 0, 0, implicit $mode, implicit $exec286 %res8:vgpr_32 = V_ADD_F32_e64 0, %res8, 0, %8, 0, 0, implicit $mode, implicit $exec287 %res9:vgpr_32 = V_ADD_F32_e64 0, %res9, 0, %9, 0, 0, implicit $mode, implicit $exec288 %res10:vgpr_32 = V_ADD_F32_e64 0, %res10, 0, %10, 0, 0, implicit $mode, implicit $exec289 %res11:vgpr_32 = V_ADD_F32_e64 0, %res11, 0, %11, 0, 0, implicit $mode, implicit $exec290 %res12:vgpr_32 = V_ADD_F32_e64 0, %res12, 0, %12, 0, 0, implicit $mode, implicit $exec291 %count:sgpr_32 = nuw nsw S_ADD_I32 %count, 1, implicit-def dead $scc292 %vcmp2:sreg_32 = V_CMP_GE_I32_e64 %count, %loop_end, implicit $exec293 %mask2:sgpr_32 = S_OR_B32 %vcmp2, %mask2, implicit-def $scc294 $exec_lo = S_ANDN2_B32_term $exec_lo, %mask2, implicit-def $scc295 S_CBRANCH_EXECNZ %bb.3, implicit $exec296 S_BRANCH %bb.4297 298 bb.4: ; flow299 successors: %bb.2(0x80000000)300 301 $exec_lo = S_OR_B32 $exec_lo, %mask2, implicit-def $scc302 S_BRANCH %bb.2303 304 bb.5: ; exit305 EXP_DONE 0, %res1, %res2, %res3, %res4, -1, 0, 15, implicit $exec306 EXP_DONE 0, %res5, %res6, %res7, %res8, -1, 0, 15, implicit $exec307 EXP_DONE 0, %res9, %res10, %res11, %res12, -1, 0, 15, implicit $exec308 S_ENDPGM 0309 310...311