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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=register-coalescer -o - %s | FileCheck %s3 4# Check that we get two move-immediates into %1 and %2, instead of a copy from5# %1 to %2, because that would introduce a dependency and maybe a stall.6---7name: remat_v_mov_b32_e328tracksRegLiveness: true9body: |10 ; CHECK-LABEL: name: remat_v_mov_b32_e3211 ; CHECK: bb.0:12 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)13 ; CHECK-NEXT: liveins: $sgpr014 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec16 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 0, implicit $exec17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr018 ; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY]]19 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec20 ; CHECK-NEXT: S_BRANCH %bb.121 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: bb.1:23 ; CHECK-NEXT: successors: %bb.2(0x80000000)24 ; CHECK-NEXT: {{ $}}25 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MUL_F32_e32 [[V_MOV_B32_e32_]].sub0, [[V_MOV_B32_e32_]].sub0, implicit $mode, implicit $exec26 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MUL_F32_e32 [[V_MOV_B32_e32_]].sub1, [[V_MOV_B32_e32_]].sub1, implicit $mode, implicit $exec27 ; CHECK-NEXT: {{ $}}28 ; CHECK-NEXT: bb.2:29 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]30 bb.0:31 liveins: $sgpr032 %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec33 %1:vgpr_32 = COPY %0:vgpr_3234 %2:vgpr_32 = COPY %0:vgpr_3235 %3:sreg_64 = COPY $sgpr036 $exec = S_MOV_B64_term %3:sreg_6437 S_CBRANCH_EXECZ %bb.2, implicit $exec38 S_BRANCH %bb.139 40 bb.1:41 %1:vgpr_32 = V_MUL_F32_e32 %1:vgpr_32, %1:vgpr_32, implicit $mode, implicit $exec42 %2:vgpr_32 = V_MUL_F32_e32 %2:vgpr_32, %2:vgpr_32, implicit $mode, implicit $exec43 44 bb.2:45 undef %4.sub0:vreg_96 = COPY %1:vgpr_3246 %4.sub1:vreg_96 = COPY %2:vgpr_3247 S_ENDPGM 0, implicit %448...49 50---51name: remat_v_mov_b64_pseudo52tracksRegLiveness: true53body: |54 ; CHECK-LABEL: name: remat_v_mov_b64_pseudo55 ; CHECK: bb.0:56 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)57 ; CHECK-NEXT: liveins: $sgpr058 ; CHECK-NEXT: {{ $}}59 ; CHECK-NEXT: undef [[V_MOV_B:%[0-9]+]].sub0_sub1:vreg_192_align2 = V_MOV_B64_PSEUDO 0, implicit $exec60 ; CHECK-NEXT: [[V_MOV_B:%[0-9]+]].sub2_sub3:vreg_192_align2 = V_MOV_B64_PSEUDO 0, implicit $exec61 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr162 ; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY]]63 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec64 ; CHECK-NEXT: S_BRANCH %bb.165 ; CHECK-NEXT: {{ $}}66 ; CHECK-NEXT: bb.1:67 ; CHECK-NEXT: successors: %bb.2(0x80000000)68 ; CHECK-NEXT: {{ $}}69 ; CHECK-NEXT: [[V_MOV_B:%[0-9]+]].sub0_sub1:vreg_192_align2 = V_MUL_F64_e64 0, [[V_MOV_B]].sub0_sub1, 0, [[V_MOV_B]].sub0_sub1, 0, 0, implicit $mode, implicit $exec70 ; CHECK-NEXT: [[V_MOV_B:%[0-9]+]].sub2_sub3:vreg_192_align2 = V_MUL_F64_e64 0, [[V_MOV_B]].sub2_sub3, 0, [[V_MOV_B]].sub2_sub3, 0, 0, implicit $mode, implicit $exec71 ; CHECK-NEXT: {{ $}}72 ; CHECK-NEXT: bb.2:73 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_MOV_B]]74 bb.0:75 liveins: $sgpr076 %0:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec77 %1:vreg_64_align2 = COPY %0:vreg_64_align278 %2:vreg_64_align2 = COPY %0:vreg_64_align279 %3:sreg_64 = COPY $sgpr0_sgpr180 $exec = S_MOV_B64_term %3:sreg_6481 S_CBRANCH_EXECZ %bb.2, implicit $exec82 S_BRANCH %bb.183 84 bb.1:85 %1:vreg_64_align2 = V_MUL_F64_e64 0, %1:vreg_64_align2, 0, %1:vreg_64_align2, 0, 0, implicit $mode, implicit $exec86 %2:vreg_64_align2 = V_MUL_F64_e64 0, %2:vreg_64_align2, 0, %2:vreg_64_align2, 0, 0, implicit $mode, implicit $exec87 88 bb.2:89 undef %4.sub0_sub1:vreg_192 = COPY %1:vreg_64_align290 %4.sub2_sub3:vreg_192 = COPY %2:vreg_64_align291 S_ENDPGM 0, implicit %492...93 94---95name: av_mov_imm_b3296tracksRegLiveness: true97body: |98 ; CHECK-LABEL: name: av_mov_imm_b3299 ; CHECK: bb.0:100 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)101 ; CHECK-NEXT: liveins: $sgpr0102 ; CHECK-NEXT: {{ $}}103 ; CHECK-NEXT: undef [[AV_MOV_:%[0-9]+]].sub0:vreg_96 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec104 ; CHECK-NEXT: [[AV_MOV_:%[0-9]+]].sub1:vreg_96 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec105 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0106 ; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY]]107 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec108 ; CHECK-NEXT: S_BRANCH %bb.1109 ; CHECK-NEXT: {{ $}}110 ; CHECK-NEXT: bb.1:111 ; CHECK-NEXT: successors: %bb.2(0x80000000)112 ; CHECK-NEXT: {{ $}}113 ; CHECK-NEXT: [[AV_MOV_:%[0-9]+]].sub0:vreg_96 = V_MUL_F32_e32 [[AV_MOV_]].sub0, [[AV_MOV_]].sub0, implicit $mode, implicit $exec114 ; CHECK-NEXT: [[AV_MOV_:%[0-9]+]].sub1:vreg_96 = V_MUL_F32_e32 [[AV_MOV_]].sub1, [[AV_MOV_]].sub1, implicit $mode, implicit $exec115 ; CHECK-NEXT: {{ $}}116 ; CHECK-NEXT: bb.2:117 ; CHECK-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]118 bb.0:119 liveins: $sgpr0120 %0:av_32 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec121 %1:vgpr_32 = COPY %0122 %2:vgpr_32 = COPY %0123 %3:sreg_64 = COPY $sgpr0124 $exec = S_MOV_B64_term %3:sreg_64125 S_CBRANCH_EXECZ %bb.2, implicit $exec126 S_BRANCH %bb.1127 128 bb.1:129 %1:vgpr_32 = V_MUL_F32_e32 %1:vgpr_32, %1:vgpr_32, implicit $mode, implicit $exec130 %2:vgpr_32 = V_MUL_F32_e32 %2:vgpr_32, %2:vgpr_32, implicit $mode, implicit $exec131 132 bb.2:133 undef %4.sub0:vreg_96 = COPY %1:vgpr_32134 %4.sub1:vreg_96 = COPY %2:vgpr_32135 S_ENDPGM 0, implicit %4136 137...138 139---140name: av_mov_imm_b64141tracksRegLiveness: true142body: |143 ; CHECK-LABEL: name: av_mov_imm_b64144 ; CHECK: bb.0:145 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)146 ; CHECK-NEXT: liveins: $sgpr0_sgpr1147 ; CHECK-NEXT: {{ $}}148 ; CHECK-NEXT: undef [[AV_MOV_:%[0-9]+]].sub0_sub1:vreg_192 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec149 ; CHECK-NEXT: [[AV_MOV_:%[0-9]+]].sub2_sub3:vreg_192 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec150 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1151 ; CHECK-NEXT: $exec = S_MOV_B64_term [[COPY]]152 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec153 ; CHECK-NEXT: S_BRANCH %bb.1154 ; CHECK-NEXT: {{ $}}155 ; CHECK-NEXT: bb.1:156 ; CHECK-NEXT: successors: %bb.2(0x80000000)157 ; CHECK-NEXT: {{ $}}158 ; CHECK-NEXT: [[AV_MOV_:%[0-9]+]].sub0_sub1:vreg_192 = V_MUL_F64_e64 0, [[AV_MOV_]].sub0_sub1, 0, [[AV_MOV_]].sub0_sub1, 0, 0, implicit $mode, implicit $exec159 ; CHECK-NEXT: [[AV_MOV_:%[0-9]+]].sub2_sub3:vreg_192 = V_MUL_F64_e64 0, [[AV_MOV_]].sub2_sub3, 0, [[AV_MOV_]].sub2_sub3, 0, 0, implicit $mode, implicit $exec160 ; CHECK-NEXT: {{ $}}161 ; CHECK-NEXT: bb.2:162 ; CHECK-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]]163 bb.0:164 liveins: $sgpr0_sgpr1165 %0:av_64 = AV_MOV_B64_IMM_PSEUDO 0, implicit $exec166 %1:vreg_64 = COPY %0167 %2:vreg_64 = COPY %0168 %3:sreg_64 = COPY $sgpr0_sgpr1169 $exec = S_MOV_B64_term %3:sreg_64170 S_CBRANCH_EXECZ %bb.2, implicit $exec171 S_BRANCH %bb.1172 173 bb.1:174 %1:vreg_64 = V_MUL_F64_e64 0, %1:vreg_64, 0, %1:vreg_64, 0, 0, implicit $mode, implicit $exec175 %2:vreg_64 = V_MUL_F64_e64 0, %2:vreg_64, 0, %2:vreg_64, 0, 0, implicit $mode, implicit $exec176 177 bb.2:178 undef %4.sub0_sub1:vreg_192 = COPY %1:vreg_64179 %4.sub2_sub3:vreg_192 = COPY %2:vreg_64180 S_ENDPGM 0, implicit %4181 182...183