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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck %s3 4@V1 = protected local_unnamed_addr addrspace(1) global i32 0, align 45@V2 = protected local_unnamed_addr addrspace(1) global i32 0, align 46@Q = internal addrspace(3) global i8 poison, align 167 8; Test spill placement of VGPR reload in %bb.194 relative to the SGPR9; reload used for the exec mask. The buffer_load_dword should be after10; the s_or_b64 exec.11define amdgpu_kernel void @__omp_offloading_16_dd2df_main_l9() {12; CHECK-LABEL: __omp_offloading_16_dd2df_main_l9:13; CHECK: ; %bb.0: ; %bb14; CHECK-NEXT: s_add_u32 s0, s0, s1715; CHECK-NEXT: s_addc_u32 s1, s1, 016; CHECK-NEXT: v_mov_b32_e32 v1, v017; CHECK-NEXT: v_mov_b32_e32 v0, 018; CHECK-NEXT: global_load_ushort v2, v0, s[4:5] offset:419; CHECK-NEXT: s_waitcnt vmcnt(0)20; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:4 ; 4-byte Folded Spill21; CHECK-NEXT: s_mov_b32 s4, 022; CHECK-NEXT: v_cmp_eq_u32_e64 s[6:7], v1, s423; CHECK-NEXT: v_mov_b32_e32 v1, 024; CHECK-NEXT: ds_write_b8 v0, v125; CHECK-NEXT: s_mov_b64 s[4:5], exec26; CHECK-NEXT: ; implicit-def: $vgpr3 : SGPR spill to VGPR lane27; CHECK-NEXT: v_writelane_b32 v3, s4, 028; CHECK-NEXT: v_writelane_b32 v3, s5, 129; CHECK-NEXT: s_or_saveexec_b64 s[8:9], -130; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], 0 ; 4-byte Folded Spill31; CHECK-NEXT: s_mov_b64 exec, s[8:9]32; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]33; CHECK-NEXT: s_mov_b64 exec, s[4:5]34; CHECK-NEXT: s_cbranch_execz .LBB0_235; CHECK-NEXT: ; %bb.1: ; %bb19336; CHECK-NEXT: .LBB0_2: ; %bb19437; CHECK-NEXT: s_or_saveexec_b64 s[8:9], -138; CHECK-NEXT: buffer_load_dword v3, off, s[0:3], 0 ; 4-byte Folded Reload39; CHECK-NEXT: s_mov_b64 exec, s[8:9]40; CHECK-NEXT: s_waitcnt vmcnt(0)41; CHECK-NEXT: v_readlane_b32 s4, v3, 042; CHECK-NEXT: v_readlane_b32 s5, v3, 143; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]44; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:4 ; 4-byte Folded Reload45; CHECK-NEXT: s_mov_b32 s4, 0xffff46; CHECK-NEXT: s_waitcnt vmcnt(0)47; CHECK-NEXT: v_and_b32_e64 v0, s4, v048; CHECK-NEXT: s_mov_b32 s4, 049; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], v0, s450; CHECK-NEXT: s_and_b64 vcc, exec, s[4:5]51; CHECK-NEXT: s_cbranch_vccnz .LBB0_452; CHECK-NEXT: ; %bb.3: ; %bb20153; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:4 ; 4-byte Folded Reload54; CHECK-NEXT: s_getpc_b64 s[4:5]55; CHECK-NEXT: s_add_u32 s4, s4, V2@rel32@lo+456; CHECK-NEXT: s_addc_u32 s5, s5, V2@rel32@hi+1257; CHECK-NEXT: v_mov_b32_e32 v0, 058; CHECK-NEXT: s_waitcnt vmcnt(0)59; CHECK-NEXT: global_store_short v0, v1, s[4:5]60; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)61; CHECK-NEXT: s_barrier62; CHECK-NEXT: s_trap 263; CHECK-NEXT: ; divergent unreachable64; CHECK-NEXT: .LBB0_4: ; %UnifiedReturnBlock65; CHECK-NEXT: s_endpgm66bb:67 %i10 = tail call i32 @llvm.amdgcn.workitem.id.x()68 %i13 = tail call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()69 %i14 = getelementptr i8, ptr addrspace(4) %i13, i64 470 %i15 = load i16, ptr addrspace(4) %i14, align 471 %i22 = icmp eq i32 %i10, 072 store i8 0, ptr addrspace(3) @Q73 br i1 %i22, label %bb193, label %bb19474 75bb193: ; preds = %bb19076 br label %bb19477 78bb194: ; preds = %bb193, %bb19079 %i196 = icmp eq i16 %i15, 080 br i1 %i196, label %bb201, label %bb20281 82bb201: ; preds = %bb19483 store i16 %i15, ptr addrspace(1) @V284 call void @llvm.amdgcn.s.barrier()85 tail call void @llvm.trap()86 unreachable87 88bb202: ; preds = %bb194, %bb170, %bb9389 ret void90}91 92declare hidden void @__keep_alive()93declare i32 @llvm.amdgcn.workitem.id.x()94declare align 4 ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()95declare void @llvm.assume(i1 noundef)96declare void @llvm.amdgcn.s.barrier()97declare void @llvm.trap()98 99