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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt -mtriple=amdgcn -mcpu=gfx906 -amdgpu-late-codegenprepare -S -o - %s | FileCheck --check-prefix=GFX906 %s3 4define amdgpu_kernel void @v3i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) {5; GFX906-LABEL: define amdgpu_kernel void @v3i8_liveout(6; GFX906-SAME: ptr addrspace(1) [[SRC1:%.*]], ptr addrspace(1) [[SRC2:%.*]], ptr addrspace(1) captures(none) [[DST:%.*]]) #[[ATTR0:[0-9]+]] {7; GFX906-NEXT: entry:8; GFX906-NEXT: [[IDX:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()9; GFX906-NEXT: [[GEP1:%.*]] = getelementptr <3 x i8>, ptr addrspace(1) [[SRC1]], i32 [[IDX]]10; GFX906-NEXT: [[VEC1:%.*]] = load <3 x i8>, ptr addrspace(1) [[GEP1]], align 411; GFX906-NEXT: [[TMP0:%.*]] = shufflevector <3 x i8> [[VEC1]], <3 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>12; GFX906-NEXT: [[VEC1_BC:%.*]] = bitcast <4 x i8> [[TMP0]] to i3213; GFX906-NEXT: [[GEP2:%.*]] = getelementptr <3 x i8>, ptr addrspace(1) [[SRC2]], i32 [[IDX]]14; GFX906-NEXT: [[VEC2:%.*]] = load <3 x i8>, ptr addrspace(1) [[GEP2]], align 415; GFX906-NEXT: [[TMP1:%.*]] = shufflevector <3 x i8> [[VEC2]], <3 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>16; GFX906-NEXT: [[VEC2_BC:%.*]] = bitcast <4 x i8> [[TMP1]] to i3217; GFX906-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX]], 1518; GFX906-NEXT: br i1 [[CMP]], label [[BB_1:%.*]], label [[BB_2:%.*]]19; GFX906: bb.1:20; GFX906-NEXT: br label [[BB_2]]21; GFX906: bb.2:22; GFX906-NEXT: [[TMP5_TC:%.*]] = phi i32 [ [[VEC1_BC]], [[ENTRY:%.*]] ], [ [[VEC2_BC]], [[BB_1]] ]23; GFX906-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP5_TC]] to i2424; GFX906-NEXT: [[TMP3:%.*]] = bitcast i24 [[TMP2]] to <3 x i8>25; GFX906-NEXT: store <3 x i8> [[TMP3]], ptr addrspace(1) [[DST]], align 426; GFX906-NEXT: ret void27;28entry:29 %idx = call i32 @llvm.amdgcn.workitem.id.x()30 %gep1 = getelementptr <3 x i8>, ptr addrspace(1) %src1, i32 %idx31 %vec1 = load <3 x i8>, ptr addrspace(1) %gep132 %gep2 = getelementptr <3 x i8>, ptr addrspace(1) %src2, i32 %idx33 %vec2 = load <3 x i8>, ptr addrspace(1) %gep234 %cmp = icmp ult i32 %idx, 1535 br i1 %cmp, label %bb.1, label %bb.236bb.1:37 br label %bb.238 39bb.2:40 %tmp5 = phi <3 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]41 store <3 x i8> %tmp5, ptr addrspace(1) %dst, align 442 ret void43}44 45define amdgpu_kernel void @v4i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) {46; GFX906-LABEL: define amdgpu_kernel void @v4i8_liveout(47; GFX906-SAME: ptr addrspace(1) [[SRC1:%.*]], ptr addrspace(1) [[SRC2:%.*]], ptr addrspace(1) captures(none) [[DST:%.*]]) #[[ATTR0]] {48; GFX906-NEXT: entry:49; GFX906-NEXT: [[IDX:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()50; GFX906-NEXT: [[GEP1:%.*]] = getelementptr <4 x i8>, ptr addrspace(1) [[SRC1]], i32 [[IDX]]51; GFX906-NEXT: [[VEC1:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP1]], align 452; GFX906-NEXT: [[VEC1_BC:%.*]] = bitcast <4 x i8> [[VEC1]] to i3253; GFX906-NEXT: [[GEP2:%.*]] = getelementptr <4 x i8>, ptr addrspace(1) [[SRC2]], i32 [[IDX]]54; GFX906-NEXT: [[VEC2:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP2]], align 455; GFX906-NEXT: [[VEC2_BC:%.*]] = bitcast <4 x i8> [[VEC2]] to i3256; GFX906-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX]], 1557; GFX906-NEXT: br i1 [[CMP]], label [[BB_1:%.*]], label [[BB_2:%.*]]58; GFX906: bb.1:59; GFX906-NEXT: br label [[BB_2]]60; GFX906: bb.2:61; GFX906-NEXT: [[TMP5_TC:%.*]] = phi i32 [ [[VEC1_BC]], [[ENTRY:%.*]] ], [ [[VEC2_BC]], [[BB_1]] ]62; GFX906-NEXT: [[TMP5_TC_BC:%.*]] = bitcast i32 [[TMP5_TC]] to <4 x i8>63; GFX906-NEXT: store <4 x i8> [[TMP5_TC_BC]], ptr addrspace(1) [[DST]], align 464; GFX906-NEXT: ret void65;66entry:67 %idx = call i32 @llvm.amdgcn.workitem.id.x()68 %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx69 %vec1 = load <4 x i8>, ptr addrspace(1) %gep170 %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx71 %vec2 = load <4 x i8>, ptr addrspace(1) %gep272 %cmp = icmp ult i32 %idx, 1573 br i1 %cmp, label %bb.1, label %bb.274bb.1:75 br label %bb.276 77bb.2:78 %tmp5 = phi <4 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]79 store <4 x i8> %tmp5, ptr addrspace(1) %dst, align 480 ret void81}82 83define amdgpu_kernel void @v5i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) {84; GFX906-LABEL: define amdgpu_kernel void @v5i8_liveout(85; GFX906-SAME: ptr addrspace(1) [[SRC1:%.*]], ptr addrspace(1) [[SRC2:%.*]], ptr addrspace(1) captures(none) [[DST:%.*]]) #[[ATTR0]] {86; GFX906-NEXT: entry:87; GFX906-NEXT: [[IDX:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()88; GFX906-NEXT: [[GEP1:%.*]] = getelementptr <5 x i8>, ptr addrspace(1) [[SRC1]], i32 [[IDX]]89; GFX906-NEXT: [[VEC1:%.*]] = load <5 x i8>, ptr addrspace(1) [[GEP1]], align 890; GFX906-NEXT: [[TMP0:%.*]] = shufflevector <5 x i8> [[VEC1]], <5 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 5, i32 5>91; GFX906-NEXT: [[VEC1_BC:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>92; GFX906-NEXT: [[GEP2:%.*]] = getelementptr <5 x i8>, ptr addrspace(1) [[SRC2]], i32 [[IDX]]93; GFX906-NEXT: [[VEC2:%.*]] = load <5 x i8>, ptr addrspace(1) [[GEP2]], align 894; GFX906-NEXT: [[TMP1:%.*]] = shufflevector <5 x i8> [[VEC2]], <5 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 5, i32 5>95; GFX906-NEXT: [[VEC2_BC:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>96; GFX906-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX]], 1597; GFX906-NEXT: br i1 [[CMP]], label [[BB_1:%.*]], label [[BB_2:%.*]]98; GFX906: bb.1:99; GFX906-NEXT: br label [[BB_2]]100; GFX906: bb.2:101; GFX906-NEXT: [[TMP5_TC:%.*]] = phi <2 x i32> [ [[VEC1_BC]], [[ENTRY:%.*]] ], [ [[VEC2_BC]], [[BB_1]] ]102; GFX906-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP5_TC]] to <8 x i8>103; GFX906-NEXT: [[TMP3:%.*]] = shufflevector <8 x i8> [[TMP2]], <8 x i8> poison, <5 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4>104; GFX906-NEXT: store <5 x i8> [[TMP3]], ptr addrspace(1) [[DST]], align 4105; GFX906-NEXT: ret void106;107entry:108 %idx = call i32 @llvm.amdgcn.workitem.id.x()109 %gep1 = getelementptr <5 x i8>, ptr addrspace(1) %src1, i32 %idx110 %vec1 = load <5 x i8>, ptr addrspace(1) %gep1111 %gep2 = getelementptr <5 x i8>, ptr addrspace(1) %src2, i32 %idx112 %vec2 = load <5 x i8>, ptr addrspace(1) %gep2113 %cmp = icmp ult i32 %idx, 15114 br i1 %cmp, label %bb.1, label %bb.2115bb.1:116 br label %bb.2117 118bb.2:119 %tmp5 = phi <5 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]120 store <5 x i8> %tmp5, ptr addrspace(1) %dst, align 4121 ret void122}123 124define amdgpu_kernel void @v8i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) {125; GFX906-LABEL: define amdgpu_kernel void @v8i8_liveout(126; GFX906-SAME: ptr addrspace(1) [[SRC1:%.*]], ptr addrspace(1) [[SRC2:%.*]], ptr addrspace(1) captures(none) [[DST:%.*]]) #[[ATTR0]] {127; GFX906-NEXT: entry:128; GFX906-NEXT: [[IDX:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()129; GFX906-NEXT: [[GEP1:%.*]] = getelementptr <8 x i8>, ptr addrspace(1) [[SRC1]], i32 [[IDX]]130; GFX906-NEXT: [[VEC1:%.*]] = load <8 x i8>, ptr addrspace(1) [[GEP1]], align 8131; GFX906-NEXT: [[VEC1_BC:%.*]] = bitcast <8 x i8> [[VEC1]] to <2 x i32>132; GFX906-NEXT: [[GEP2:%.*]] = getelementptr <8 x i8>, ptr addrspace(1) [[SRC2]], i32 [[IDX]]133; GFX906-NEXT: [[VEC2:%.*]] = load <8 x i8>, ptr addrspace(1) [[GEP2]], align 8134; GFX906-NEXT: [[VEC2_BC:%.*]] = bitcast <8 x i8> [[VEC2]] to <2 x i32>135; GFX906-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX]], 15136; GFX906-NEXT: br i1 [[CMP]], label [[BB_1:%.*]], label [[BB_2:%.*]]137; GFX906: bb.1:138; GFX906-NEXT: br label [[BB_2]]139; GFX906: bb.2:140; GFX906-NEXT: [[TMP5_TC:%.*]] = phi <2 x i32> [ [[VEC1_BC]], [[ENTRY:%.*]] ], [ [[VEC2_BC]], [[BB_1]] ]141; GFX906-NEXT: [[TMP5_TC_BC:%.*]] = bitcast <2 x i32> [[TMP5_TC]] to <8 x i8>142; GFX906-NEXT: store <8 x i8> [[TMP5_TC_BC]], ptr addrspace(1) [[DST]], align 4143; GFX906-NEXT: ret void144;145entry:146 %idx = call i32 @llvm.amdgcn.workitem.id.x()147 %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx148 %vec1 = load <8 x i8>, ptr addrspace(1) %gep1149 %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx150 %vec2 = load <8 x i8>, ptr addrspace(1) %gep2151 %cmp = icmp ult i32 %idx, 15152 br i1 %cmp, label %bb.1, label %bb.2153bb.1:154 br label %bb.2155 156bb.2:157 %tmp5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]158 store <8 x i8> %tmp5, ptr addrspace(1) %dst, align 4159 ret void160}161 162define amdgpu_kernel void @repeat_successor(i32 %in, ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) {163; GFX906-LABEL: define amdgpu_kernel void @repeat_successor(164; GFX906-SAME: i32 [[IN:%.*]], ptr addrspace(1) [[SRC1:%.*]], ptr addrspace(1) [[SRC2:%.*]], ptr addrspace(1) captures(none) [[DST:%.*]]) #[[ATTR0]] {165; GFX906-NEXT: entry:166; GFX906-NEXT: [[IDX:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()167; GFX906-NEXT: [[GEP1:%.*]] = getelementptr <4 x i8>, ptr addrspace(1) [[SRC1]], i32 [[IDX]]168; GFX906-NEXT: [[VEC1:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP1]], align 4169; GFX906-NEXT: [[VEC1_BC:%.*]] = bitcast <4 x i8> [[VEC1]] to i32170; GFX906-NEXT: [[GEP2:%.*]] = getelementptr <4 x i8>, ptr addrspace(1) [[SRC2]], i32 [[IDX]]171; GFX906-NEXT: [[VEC2:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP2]], align 4172; GFX906-NEXT: [[VEC2_BC:%.*]] = bitcast <4 x i8> [[VEC2]] to i32173; GFX906-NEXT: switch i32 [[IN]], label [[RETURN:%.*]] [174; GFX906-NEXT: i32 1, label [[RETURN_SINK_SPLIT:%.*]]175; GFX906-NEXT: i32 2, label [[RETURN_SINK_SPLIT]]176; GFX906-NEXT: i32 3, label [[SW_BB5:%.*]]177; GFX906-NEXT: ]178; GFX906: sw.bb5:179; GFX906-NEXT: br label [[RETURN_SINK_SPLIT]]180; GFX906: return.sink.split:181; GFX906-NEXT: [[TMP5_TC:%.*]] = phi i32 [ [[VEC2_BC]], [[SW_BB5]] ], [ [[VEC1_BC]], [[ENTRY:%.*]] ], [ [[VEC1_BC]], [[ENTRY]] ]182; GFX906-NEXT: [[TMP5_TC_BC:%.*]] = bitcast i32 [[TMP5_TC]] to <4 x i8>183; GFX906-NEXT: store <4 x i8> [[TMP5_TC_BC]], ptr addrspace(1) [[DST]], align 4184; GFX906-NEXT: ret void185; GFX906: return:186; GFX906-NEXT: ret void187;188entry:189 %idx = call i32 @llvm.amdgcn.workitem.id.x()190 %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx191 %vec1 = load <4 x i8>, ptr addrspace(1) %gep1192 %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx193 %vec2 = load <4 x i8>, ptr addrspace(1) %gep2194 switch i32 %in, label %return [195 i32 1, label %return.sink.split196 i32 2, label %return.sink.split197 i32 3, label %sw.bb5198 ]199 200sw.bb5:201 br label %return.sink.split202 203return.sink.split:204 %tmp5 = phi <4 x i8> [ %vec2, %sw.bb5 ], [ %vec1, %entry ], [ %vec1, %entry ]205 store <4 x i8> %tmp5, ptr addrspace(1) %dst, align 4206 ret void207 208return:209 ret void210}211 212define amdgpu_kernel void @v8i8_phi_chain(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst0, ptr addrspace(1) nocapture %dst1) {213; GFX906-LABEL: define amdgpu_kernel void @v8i8_phi_chain(214; GFX906-SAME: ptr addrspace(1) [[SRC1:%.*]], ptr addrspace(1) [[SRC2:%.*]], ptr addrspace(1) captures(none) [[DST0:%.*]], ptr addrspace(1) captures(none) [[DST1:%.*]]) #[[ATTR0]] {215; GFX906-NEXT: entry:216; GFX906-NEXT: [[IDX:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()217; GFX906-NEXT: [[GEP1:%.*]] = getelementptr <8 x i8>, ptr addrspace(1) [[SRC1]], i32 [[IDX]]218; GFX906-NEXT: [[VEC1:%.*]] = load <8 x i8>, ptr addrspace(1) [[GEP1]], align 8219; GFX906-NEXT: [[VEC1_BC:%.*]] = bitcast <8 x i8> [[VEC1]] to <2 x i32>220; GFX906-NEXT: [[GEP2:%.*]] = getelementptr <8 x i8>, ptr addrspace(1) [[SRC2]], i32 [[IDX]]221; GFX906-NEXT: [[VEC2:%.*]] = load <8 x i8>, ptr addrspace(1) [[GEP2]], align 8222; GFX906-NEXT: [[VEC2_BC:%.*]] = bitcast <8 x i8> [[VEC2]] to <2 x i32>223; GFX906-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX]], 15224; GFX906-NEXT: br i1 [[CMP]], label [[BB_1:%.*]], label [[BB_2:%.*]]225; GFX906: bb.1:226; GFX906-NEXT: [[CMP2:%.*]] = icmp ult i32 [[IDX]], 7227; GFX906-NEXT: br i1 [[CMP2]], label [[BB_2]], label [[BB_3:%.*]]228; GFX906: bb.2:229; GFX906-NEXT: [[TMP5_TC:%.*]] = phi <2 x i32> [ [[VEC1_BC]], [[ENTRY:%.*]] ], [ [[VEC2_BC]], [[BB_1]] ]230; GFX906-NEXT: [[TMP5_TC_BC:%.*]] = bitcast <2 x i32> [[TMP5_TC]] to <8 x i8>231; GFX906-NEXT: store <8 x i8> [[TMP5_TC_BC]], ptr addrspace(1) [[DST0]], align 4232; GFX906-NEXT: br label [[BB_3]]233; GFX906: bb.3:234; GFX906-NEXT: [[TMP7_TC:%.*]] = phi <2 x i32> [ [[VEC2_BC]], [[BB_1]] ], [ [[TMP5_TC]], [[BB_2]] ]235; GFX906-NEXT: [[TMP7_TC_BC:%.*]] = bitcast <2 x i32> [[TMP7_TC]] to <8 x i8>236; GFX906-NEXT: store <8 x i8> [[TMP7_TC_BC]], ptr addrspace(1) [[DST1]], align 4237; GFX906-NEXT: ret void238;239entry:240 %idx = call i32 @llvm.amdgcn.workitem.id.x()241 %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx242 %vec1 = load <8 x i8>, ptr addrspace(1) %gep1243 %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx244 %vec2 = load <8 x i8>, ptr addrspace(1) %gep2245 %cmp = icmp ult i32 %idx, 15246 br i1 %cmp, label %bb.1, label %bb.2247bb.1:248 %cmp2 = icmp ult i32 %idx, 7249 br i1 %cmp2, label %bb.2, label %bb.3250 251bb.2:252 %tmp5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]253 store <8 x i8> %tmp5, ptr addrspace(1) %dst0, align 4254 br label %bb.3255 256bb.3:257 %tmp7 = phi <8 x i8> [ %vec2, %bb.1], [%tmp5, %bb.2]258 store <8 x i8> %tmp7, ptr addrspace(1) %dst1, align 4259 ret void260}261 262define amdgpu_kernel void @v8i8_multi_block(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst0, ptr addrspace(1) nocapture %dst1) {263; GFX906-LABEL: define amdgpu_kernel void @v8i8_multi_block(264; GFX906-SAME: ptr addrspace(1) [[SRC1:%.*]], ptr addrspace(1) [[SRC2:%.*]], ptr addrspace(1) captures(none) [[DST0:%.*]], ptr addrspace(1) captures(none) [[DST1:%.*]]) #[[ATTR0]] {265; GFX906-NEXT: entry:266; GFX906-NEXT: [[IDX:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()267; GFX906-NEXT: [[GEP1:%.*]] = getelementptr <8 x i8>, ptr addrspace(1) [[SRC1]], i32 [[IDX]]268; GFX906-NEXT: [[VEC1:%.*]] = load <8 x i8>, ptr addrspace(1) [[GEP1]], align 8269; GFX906-NEXT: [[VEC1_BC:%.*]] = bitcast <8 x i8> [[VEC1]] to <2 x i32>270; GFX906-NEXT: [[GEP2:%.*]] = getelementptr <8 x i8>, ptr addrspace(1) [[SRC2]], i32 [[IDX]]271; GFX906-NEXT: [[VEC2:%.*]] = load <8 x i8>, ptr addrspace(1) [[GEP2]], align 8272; GFX906-NEXT: [[VEC2_BC:%.*]] = bitcast <8 x i8> [[VEC2]] to <2 x i32>273; GFX906-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX]], 15274; GFX906-NEXT: br i1 [[CMP]], label [[BB_1:%.*]], label [[BB_3:%.*]]275; GFX906: bb.1:276; GFX906-NEXT: [[CMP2:%.*]] = icmp ult i32 [[IDX]], 7277; GFX906-NEXT: br i1 [[CMP2]], label [[BB_2:%.*]], label [[BB_3]]278; GFX906: bb.2:279; GFX906-NEXT: [[VEC1_BC_BC:%.*]] = bitcast <2 x i32> [[VEC1_BC]] to <8 x i8>280; GFX906-NEXT: store <8 x i8> [[VEC1_BC_BC]], ptr addrspace(1) [[DST0]], align 4281; GFX906-NEXT: br label [[BB_3]]282; GFX906: bb.3:283; GFX906-NEXT: [[TMP5_TC:%.*]] = phi <2 x i32> [ [[VEC1_BC]], [[ENTRY:%.*]] ], [ [[VEC2_BC]], [[BB_1]] ], [ [[VEC2_BC]], [[BB_2]] ]284; GFX906-NEXT: [[TMP5_TC_BC:%.*]] = bitcast <2 x i32> [[TMP5_TC]] to <8 x i8>285; GFX906-NEXT: store <8 x i8> [[TMP5_TC_BC]], ptr addrspace(1) [[DST1]], align 4286; GFX906-NEXT: ret void287;288entry:289 %idx = call i32 @llvm.amdgcn.workitem.id.x()290 %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx291 %vec1 = load <8 x i8>, ptr addrspace(1) %gep1292 %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx293 %vec2 = load <8 x i8>, ptr addrspace(1) %gep2294 %cmp = icmp ult i32 %idx, 15295 br i1 %cmp, label %bb.1, label %bb.3296bb.1:297 %cmp2 = icmp ult i32 %idx, 7298 br i1 %cmp2, label %bb.2, label %bb.3299 300bb.2:301 store <8 x i8> %vec1, ptr addrspace(1) %dst0, align 4302 br label %bb.3303 304bb.3:305 %tmp5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ], [ %vec2, %bb.2]306 store <8 x i8> %tmp5, ptr addrspace(1) %dst1, align 4307 ret void308}309 310define amdgpu_kernel void @v32i8_loop_carried(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) {311; GFX906-LABEL: define amdgpu_kernel void @v32i8_loop_carried(312; GFX906-SAME: ptr addrspace(1) [[SRC1:%.*]], ptr addrspace(1) [[SRC2:%.*]], ptr addrspace(1) captures(none) [[DST:%.*]]) #[[ATTR0]] {313; GFX906-NEXT: entry:314; GFX906-NEXT: [[IDX:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()315; GFX906-NEXT: [[GEP1:%.*]] = getelementptr <32 x i8>, ptr addrspace(1) [[SRC1]], i32 [[IDX]]316; GFX906-NEXT: [[VEC1:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP1]], align 4317; GFX906-NEXT: [[VEC1_BC:%.*]] = bitcast <4 x i8> [[VEC1]] to i32318; GFX906-NEXT: br label [[BB_1:%.*]]319; GFX906: bb.1:320; GFX906-NEXT: [[TEMP_TC:%.*]] = phi i32 [ [[VEC1_BC]], [[ENTRY:%.*]] ], [ [[VEC2_BC:%.*]], [[BB_1]] ]321; GFX906-NEXT: [[TEMP_TC_BC:%.*]] = bitcast i32 [[TEMP_TC]] to <4 x i8>322; GFX906-NEXT: [[VEC1_BC_BC:%.*]] = bitcast i32 [[VEC1_BC]] to <4 x i8>323; GFX906-NEXT: [[VEC2:%.*]] = shufflevector <4 x i8> [[VEC1_BC_BC]], <4 x i8> [[TEMP_TC_BC]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>324; GFX906-NEXT: [[VEC2_BC]] = bitcast <4 x i8> [[VEC2]] to i32325; GFX906-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX]], 15326; GFX906-NEXT: br i1 [[CMP]], label [[BB_1]], label [[BB_2:%.*]]327; GFX906: 0:328; GFX906-NEXT: br label [[BB_2]]329; GFX906: bb.2:330; GFX906-NEXT: [[VEC2_BC_BC:%.*]] = bitcast i32 [[VEC2_BC]] to <4 x i8>331; GFX906-NEXT: store <4 x i8> [[VEC2_BC_BC]], ptr addrspace(1) [[DST]], align 4332; GFX906-NEXT: ret void333;334entry:335 %idx = call i32 @llvm.amdgcn.workitem.id.x()336 %gep1 = getelementptr <32 x i8>, ptr addrspace(1) %src1, i32 %idx337 %vec1 = load <4 x i8>, ptr addrspace(1) %gep1338 br label %bb.1339 340bb.1:341 %temp = phi <4 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]342 %vec2 = shufflevector <4 x i8> %vec1, <4 x i8> %temp, <4 x i32> <i32 0, i32 2, i32 4, i32 6>343 %cmp = icmp ult i32 %idx, 15344 br i1 %cmp, label %bb.1, label %bb.2345 br label %bb.2346 347bb.2:348 store <4 x i8> %vec2, ptr addrspace(1) %dst, align 4349 ret void350}351 352; Should not produce a broken phi353 354define void @broken_phi() {355; GFX906-LABEL: define void @broken_phi(356; GFX906-SAME: ) #[[ATTR0]] {357; GFX906-NEXT: bb:358; GFX906-NEXT: br label [[BB1:%.*]]359; GFX906: bb1:360; GFX906-NEXT: [[I:%.*]] = phi <4 x i8> [ splat (i8 1), [[BB:%.*]] ], [ [[I8:%.*]], [[BB7:%.*]] ]361; GFX906-NEXT: br i1 false, label [[BB3:%.*]], label [[BB2:%.*]]362; GFX906: bb2:363; GFX906-NEXT: br label [[BB3]]364; GFX906: bb3:365; GFX906-NEXT: [[I4:%.*]] = phi <4 x i8> [ zeroinitializer, [[BB2]] ], [ [[I]], [[BB1]] ]366; GFX906-NEXT: br i1 false, label [[BB7]], label [[BB5:%.*]]367; GFX906: bb5:368; GFX906-NEXT: [[I6:%.*]] = call <4 x i8> @llvm.smax.v4i8(<4 x i8> [[I4]], <4 x i8> zeroinitializer)369; GFX906-NEXT: br label [[BB7]]370; GFX906: bb7:371; GFX906-NEXT: [[I8]] = phi <4 x i8> [ zeroinitializer, [[BB5]] ], [ zeroinitializer, [[BB3]] ]372; GFX906-NEXT: br label [[BB1]]373;374bb:375 br label %bb1376bb1:377 %i = phi <4 x i8> [ <i8 1, i8 1, i8 1, i8 1>, %bb ], [ %i8, %bb7 ]378 br i1 false, label %bb3, label %bb2379bb2:380 br label %bb3381bb3:382 %i4 = phi <4 x i8> [ zeroinitializer, %bb2 ], [ %i, %bb1 ]383 br i1 false, label %bb7, label %bb5384bb5:385 %i6 = call <4 x i8> @llvm.smax.v4i8(<4 x i8> %i4, <4 x i8> zeroinitializer)386 br label %bb7387bb7:388 %i8 = phi <4 x i8> [ zeroinitializer, %bb5 ], [ zeroinitializer, %bb3 ]389 br label %bb1390}391 392; %sel1 should just use %sel0 instead of trying to convert back the393; converted version of %sel0394 395define amdgpu_kernel void @reuseOp() {396; GFX906-LABEL: define amdgpu_kernel void @reuseOp(397; GFX906-SAME: ) #[[ATTR0]] {398; GFX906-NEXT: entry:399; GFX906-NEXT: [[VEC1:%.*]] = insertelement <16 x i8> zeroinitializer, i8 0, i64 0400; GFX906-NEXT: br label [[BB_1:%.*]]401; GFX906: bb.1:402; GFX906-NEXT: [[SEL0:%.*]] = select i1 false, <16 x i8> zeroinitializer, <16 x i8> zeroinitializer403; GFX906-NEXT: [[SEL1:%.*]] = select i1 false, <16 x i8> [[VEC1]], <16 x i8> [[SEL0]]404; GFX906-NEXT: br label [[BB_2:%.*]]405; GFX906: bb.2:406; GFX906-NEXT: [[VAL:%.*]] = extractelement <16 x i8> [[SEL0]], i64 0407; GFX906-NEXT: ret void408;409entry:410 %vec1 = insertelement <16 x i8> zeroinitializer, i8 0, i64 0411 br label %bb.1412 413bb.1:414 %sel0 = select i1 false, <16 x i8> zeroinitializer, <16 x i8> zeroinitializer415 %sel1 = select i1 false, <16 x i8> %vec1, <16 x i8> %sel0416 br label %bb.2417 418bb.2:419 %val = extractelement <16 x i8> %sel0, i64 0420 ret void421}422 423 424define amdgpu_kernel void @deletedPHI(i32 %in0, i1 %cmp, <10 x i8> %invec0) {425; GFX906-LABEL: define amdgpu_kernel void @deletedPHI(426; GFX906-SAME: i32 [[IN0:%.*]], i1 [[CMP:%.*]], <10 x i8> [[INVEC0:%.*]]) #[[ATTR0]] {427; GFX906-NEXT: entry:428; GFX906-NEXT: br label [[BB_1:%.*]]429; GFX906: bb.1:430; GFX906-NEXT: [[PHI0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ 1, [[BB_11:%.*]] ]431; GFX906-NEXT: [[PHI1:%.*]] = phi <10 x i8> [ splat (i8 1), [[ENTRY]] ], [ [[VEC1:%.*]], [[BB_11]] ]432; GFX906-NEXT: br i1 [[CMP]], label [[BB_3:%.*]], label [[BB_2:%.*]]433; GFX906: bb.2:434; GFX906-NEXT: br label [[BB_3]]435; GFX906: bb.3:436; GFX906-NEXT: [[PHI2:%.*]] = phi <10 x i8> [ zeroinitializer, [[BB_2]] ], [ [[PHI1]], [[BB_1]] ]437; GFX906-NEXT: br i1 [[CMP]], label [[BB_5:%.*]], label [[BB_4:%.*]]438; GFX906: bb.4:439; GFX906-NEXT: [[VEC0:%.*]] = insertelement <10 x i8> [[PHI2]], i8 0, i64 0440; GFX906-NEXT: br label [[BB_5]]441; GFX906: bb.5:442; GFX906-NEXT: [[PHI3:%.*]] = phi <10 x i8> [ [[VEC0]], [[BB_4]] ], [ [[PHI2]], [[BB_3]] ]443; GFX906-NEXT: br i1 [[CMP]], label [[BB_7:%.*]], label [[BB_6:%.*]]444; GFX906: bb.6:445; GFX906-NEXT: br label [[BB_7]]446; GFX906: bb.7:447; GFX906-NEXT: [[PHI4:%.*]] = phi <10 x i8> [ [[INVEC0]], [[BB_6]] ], [ [[PHI3]], [[BB_5]] ]448; GFX906-NEXT: br i1 [[CMP]], label [[BB_9:%.*]], label [[BB_8:%.*]]449; GFX906: bb.8:450; GFX906-NEXT: br label [[BB_9]]451; GFX906: bb.9:452; GFX906-NEXT: [[PHI5:%.*]] = phi <10 x i8> [ [[INVEC0]], [[BB_8]] ], [ [[PHI4]], [[BB_7]] ]453; GFX906-NEXT: br i1 [[CMP]], label [[BB_11]], label [[BB_10:%.*]]454; GFX906: bb.10:455; GFX906-NEXT: br label [[BB_11]]456; GFX906: bb.11:457; GFX906-NEXT: [[PHI6:%.*]] = phi <10 x i8> [ zeroinitializer, [[BB_10]] ], [ [[PHI5]], [[BB_9]] ]458; GFX906-NEXT: [[VEC1]] = shufflevector <10 x i8> [[PHI6]], <10 x i8> zeroinitializer, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 15, i32 16, i32 17, i32 18, i32 19>459; GFX906-NEXT: br label [[BB_1]]460;461entry:462 br label %bb.1463 464bb.1:465 %phi0 = phi i32 [ 0, %entry ], [ 1, %bb.11 ]466 %phi1 = phi <10 x i8> [ <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, %entry ], [ %vec1, %bb.11 ]467 br i1 %cmp, label %bb.3, label %bb.2468 469bb.2:470 br label %bb.3471 472bb.3:473 %phi2 = phi <10 x i8> [ zeroinitializer, %bb.2 ], [ %phi1, %bb.1 ]474 br i1 %cmp, label %bb.5, label %bb.4475 476bb.4:477 %vec0 = insertelement <10 x i8> %phi2, i8 0, i64 0478 br label %bb.5479 480bb.5: ; preds = %bb.4, %bb.3481 %phi3 = phi <10 x i8> [ %vec0, %bb.4 ], [ %phi2, %bb.3 ]482 br i1 %cmp, label %bb.7, label %bb.6483 484bb.6:485 br label %bb.7486 487bb.7: ; preds = %bb.6, %bb.5488 %phi4 = phi <10 x i8> [ %invec0, %bb.6 ], [ %phi3, %bb.5 ]489 br i1 %cmp, label %bb.9, label %bb.8490 491bb.8:492 br label %bb.9493 494bb.9:495 %phi5 = phi <10 x i8> [ %invec0, %bb.8 ], [ %phi4, %bb.7 ]496 br i1 %cmp, label %bb.11, label %bb.10497 498bb.10:499 br label %bb.11500 501bb.11:502 %phi6 = phi <10 x i8> [ zeroinitializer, %bb.10 ], [ %phi5, %bb.9 ]503 %vec1 = shufflevector <10 x i8> %phi6, <10 x i8> zeroinitializer, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 15, i32 16, i32 17, i32 18, i32 19>504 br label %bb.1505}506 507define amdgpu_kernel void @multiple_unwind(i1 %cmp, <10 x i8> %invec) {508; GFX906-LABEL: define amdgpu_kernel void @multiple_unwind(509; GFX906-SAME: i1 [[CMP:%.*]], <10 x i8> [[INVEC:%.*]]) #[[ATTR0]] {510; GFX906-NEXT: entry:511; GFX906-NEXT: br label [[BB_1:%.*]]512; GFX906: bb.1:513; GFX906-NEXT: [[PHI0:%.*]] = phi <10 x i8> [ splat (i8 1), [[ENTRY:%.*]] ], [ [[PHI3:%.*]], [[BB_8:%.*]] ]514; GFX906-NEXT: br i1 [[CMP]], label [[BB_3:%.*]], label [[BB_2:%.*]]515; GFX906: bb.2:516; GFX906-NEXT: br label [[BB_3]]517; GFX906: bb.3:518; GFX906-NEXT: [[PHI1:%.*]] = phi <10 x i8> [ zeroinitializer, [[BB_2]] ], [ [[PHI0]], [[BB_1]] ]519; GFX906-NEXT: br i1 [[CMP]], label [[BB_5:%.*]], label [[BB_4:%.*]]520; GFX906: bb.4:521; GFX906-NEXT: br label [[BB_5]]522; GFX906: bb.5:523; GFX906-NEXT: [[PHI2:%.*]] = phi <10 x i8> [ [[PHI0]], [[BB_4]] ], [ [[PHI1]], [[BB_3]] ]524; GFX906-NEXT: br i1 [[CMP]], label [[BB_7:%.*]], label [[BB_6:%.*]]525; GFX906: bb.6:526; GFX906-NEXT: br label [[BB_7]]527; GFX906: bb.7:528; GFX906-NEXT: [[PHI3]] = phi <10 x i8> [ [[INVEC]], [[BB_6]] ], [ [[PHI2]], [[BB_5]] ]529; GFX906-NEXT: br label [[BB_8]]530; GFX906: bb.8:531; GFX906-NEXT: br label [[BB_1]]532;533entry:534 br label %bb.1535 536bb.1:537 %phi0 = phi <10 x i8> [ <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, %entry ], [ %phi3, %bb.8 ]538 br i1 %cmp, label %bb.3, label %bb.2539 540bb.2:541 br label %bb.3542 543bb.3:544 %phi1 = phi <10 x i8> [ zeroinitializer, %bb.2 ], [ %phi0, %bb.1 ]545 br i1 %cmp, label %bb.5, label %bb.4546 547bb.4:548 br label %bb.5549 550bb.5:551 %phi2 = phi <10 x i8> [ %phi0, %bb.4 ], [ %phi1, %bb.3 ]552 br i1 %cmp, label %bb.7, label %bb.6553 554bb.6: ; preds = %bb.5555 br label %bb.7556 557bb.7:558 %phi3 = phi <10 x i8> [ %invec, %bb.6 ], [ %phi2, %bb.5 ]559 br label %bb.8560 561bb.8:562 br label %bb.1563}564 565 566 567declare i32 @llvm.amdgcn.workitem.id.x()568