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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52;RUN: llc < %s -mtriple=amdgcn | FileCheck --check-prefixes=SI %s3;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck --check-prefixes=VI %s4;RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck --check-prefixes=EG %s5 6define amdgpu_kernel void @test_select_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1, <2 x i32> %val) {7; SI-LABEL: test_select_v2i32:8; SI: ; %bb.0: ; %entry9; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x910; SI-NEXT: s_waitcnt lgkmcnt(0)11; SI-NEXT: s_load_dwordx2 s[8:9], s[2:3], 0x012; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x013; SI-NEXT: s_mov_b32 s3, 0xf00014; SI-NEXT: s_waitcnt lgkmcnt(0)15; SI-NEXT: s_cmp_gt_i32 s9, s516; SI-NEXT: s_cselect_b32 s5, s7, s917; SI-NEXT: s_cmp_gt_i32 s8, s418; SI-NEXT: s_cselect_b32 s4, s6, s819; SI-NEXT: s_mov_b32 s2, -120; SI-NEXT: v_mov_b32_e32 v1, s521; SI-NEXT: v_mov_b32_e32 v0, s422; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 023; SI-NEXT: s_endpgm24;25; VI-LABEL: test_select_v2i32:26; VI: ; %bb.0: ; %entry27; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x2428; VI-NEXT: s_waitcnt lgkmcnt(0)29; VI-NEXT: s_load_dwordx2 s[8:9], s[2:3], 0x030; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x031; VI-NEXT: s_mov_b32 s3, 0xf00032; VI-NEXT: s_mov_b32 s2, -133; VI-NEXT: s_waitcnt lgkmcnt(0)34; VI-NEXT: s_cmp_gt_i32 s9, s535; VI-NEXT: s_cselect_b32 s5, s7, s936; VI-NEXT: s_cmp_gt_i32 s8, s437; VI-NEXT: s_cselect_b32 s4, s6, s838; VI-NEXT: v_mov_b32_e32 v0, s439; VI-NEXT: v_mov_b32_e32 v1, s540; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 041; VI-NEXT: s_endpgm42;43; EG-LABEL: test_select_v2i32:44; EG: ; %bb.0: ; %entry45; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]46; EG-NEXT: TEX 1 @647; EG-NEXT: ALU 5, @12, KC0[CB0:0-32], KC1[]48; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 149; EG-NEXT: CF_END50; EG-NEXT: PAD51; EG-NEXT: Fetch clause starting at 6:52; EG-NEXT: VTX_READ_64 T1.XY, T1.X, 0, #153; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #154; EG-NEXT: ALU clause starting at 10:55; EG-NEXT: MOV T0.X, KC0[2].Z,56; EG-NEXT: MOV * T1.X, KC0[2].W,57; EG-NEXT: ALU clause starting at 12:58; EG-NEXT: SETGT_INT * T0.W, T0.Y, T1.Y,59; EG-NEXT: CNDE_INT T0.Y, PV.W, T0.Y, KC0[3].Z,60; EG-NEXT: SETGT_INT * T0.W, T0.X, T1.X,61; EG-NEXT: CNDE_INT T0.X, PV.W, T0.X, KC0[3].Y,62; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,63; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)64entry:65 %load0 = load <2 x i32>, ptr addrspace(1) %in066 %load1 = load <2 x i32>, ptr addrspace(1) %in167 %cmp = icmp sgt <2 x i32> %load0, %load168 %result = select <2 x i1> %cmp, <2 x i32> %val, <2 x i32> %load069 store <2 x i32> %result, ptr addrspace(1) %out70 ret void71}72 73define amdgpu_kernel void @test_select_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {74; SI-LABEL: test_select_v2f32:75; SI: ; %bb.0: ; %entry76; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x977; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd78; SI-NEXT: s_waitcnt lgkmcnt(0)79; SI-NEXT: s_load_dwordx2 s[6:7], s[2:3], 0x080; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x081; SI-NEXT: s_mov_b32 s3, 0xf00082; SI-NEXT: s_mov_b32 s2, -183; SI-NEXT: s_waitcnt lgkmcnt(0)84; SI-NEXT: v_mov_b32_e32 v0, s485; SI-NEXT: v_mov_b32_e32 v1, s586; SI-NEXT: v_mov_b32_e32 v2, s787; SI-NEXT: v_cmp_neq_f32_e32 vcc, s7, v188; SI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc89; SI-NEXT: v_mov_b32_e32 v2, s690; SI-NEXT: v_cmp_neq_f32_e32 vcc, s6, v091; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc92; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 093; SI-NEXT: s_endpgm94;95; VI-LABEL: test_select_v2f32:96; VI: ; %bb.0: ; %entry97; VI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x3498; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2499; VI-NEXT: s_mov_b32 s7, 0xf000100; VI-NEXT: s_mov_b32 s6, -1101; VI-NEXT: s_waitcnt lgkmcnt(0)102; VI-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x0103; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0104; VI-NEXT: s_mov_b32 s4, s0105; VI-NEXT: s_mov_b32 s5, s1106; VI-NEXT: s_waitcnt lgkmcnt(0)107; VI-NEXT: v_mov_b32_e32 v1, s9108; VI-NEXT: v_mov_b32_e32 v0, s8109; VI-NEXT: v_mov_b32_e32 v2, s3110; VI-NEXT: v_cmp_neq_f32_e32 vcc, s3, v1111; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc112; VI-NEXT: v_mov_b32_e32 v2, s2113; VI-NEXT: v_cmp_neq_f32_e32 vcc, s2, v0114; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc115; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0116; VI-NEXT: s_endpgm117;118; EG-LABEL: test_select_v2f32:119; EG: ; %bb.0: ; %entry120; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]121; EG-NEXT: TEX 1 @6122; EG-NEXT: ALU 5, @12, KC0[CB0:0-32], KC1[]123; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1124; EG-NEXT: CF_END125; EG-NEXT: PAD126; EG-NEXT: Fetch clause starting at 6:127; EG-NEXT: VTX_READ_64 T1.XY, T1.X, 0, #1128; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1129; EG-NEXT: ALU clause starting at 10:130; EG-NEXT: MOV T0.X, KC0[2].Z,131; EG-NEXT: MOV * T1.X, KC0[2].W,132; EG-NEXT: ALU clause starting at 12:133; EG-NEXT: SETNE_DX10 * T0.W, T0.Y, T1.Y,134; EG-NEXT: CNDE_INT T0.Y, PV.W, T1.Y, T0.Y,135; EG-NEXT: SETNE_DX10 * T0.W, T0.X, T1.X,136; EG-NEXT: CNDE_INT T0.X, PV.W, T1.X, T0.X,137; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,138; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)139entry:140 %0 = load <2 x float>, ptr addrspace(1) %in0141 %1 = load <2 x float>, ptr addrspace(1) %in1142 %cmp = fcmp une <2 x float> %0, %1143 %result = select <2 x i1> %cmp, <2 x float> %0, <2 x float> %1144 store <2 x float> %result, ptr addrspace(1) %out145 ret void146}147 148define amdgpu_kernel void @test_select_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1, <4 x i32> %val) {149; SI-LABEL: test_select_v4i32:150; SI: ; %bb.0: ; %entry151; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9152; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xd153; SI-NEXT: s_waitcnt lgkmcnt(0)154; SI-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0155; SI-NEXT: s_load_dwordx4 s[12:15], s[6:7], 0x0156; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x11157; SI-NEXT: s_mov_b32 s3, 0xf000158; SI-NEXT: s_waitcnt lgkmcnt(0)159; SI-NEXT: s_cmp_gt_i32 s10, s14160; SI-NEXT: s_cselect_b32 s6, s6, s10161; SI-NEXT: s_cmp_gt_i32 s9, s13162; SI-NEXT: s_cselect_b32 s5, s5, s9163; SI-NEXT: s_cmp_gt_i32 s11, s15164; SI-NEXT: s_cselect_b32 s7, s7, s11165; SI-NEXT: s_cmp_gt_i32 s8, s12166; SI-NEXT: s_cselect_b32 s4, s4, s8167; SI-NEXT: s_mov_b32 s2, -1168; SI-NEXT: v_mov_b32_e32 v2, s6169; SI-NEXT: v_mov_b32_e32 v1, s5170; SI-NEXT: v_mov_b32_e32 v3, s7171; SI-NEXT: v_mov_b32_e32 v0, s4172; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0173; SI-NEXT: s_endpgm174;175; VI-LABEL: test_select_v4i32:176; VI: ; %bb.0: ; %entry177; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24178; VI-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x34179; VI-NEXT: s_mov_b32 s7, 0xf000180; VI-NEXT: s_mov_b32 s6, -1181; VI-NEXT: s_waitcnt lgkmcnt(0)182; VI-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0183; VI-NEXT: s_load_dwordx4 s[12:15], s[12:13], 0x0184; VI-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x44185; VI-NEXT: s_mov_b32 s4, s0186; VI-NEXT: s_mov_b32 s5, s1187; VI-NEXT: s_waitcnt lgkmcnt(0)188; VI-NEXT: s_cmp_gt_i32 s10, s14189; VI-NEXT: s_cselect_b32 s0, s18, s10190; VI-NEXT: s_cmp_gt_i32 s9, s13191; VI-NEXT: s_cselect_b32 s1, s17, s9192; VI-NEXT: s_cmp_gt_i32 s11, s15193; VI-NEXT: s_cselect_b32 s2, s19, s11194; VI-NEXT: s_cmp_gt_i32 s8, s12195; VI-NEXT: s_cselect_b32 s3, s16, s8196; VI-NEXT: v_mov_b32_e32 v0, s3197; VI-NEXT: v_mov_b32_e32 v1, s1198; VI-NEXT: v_mov_b32_e32 v2, s0199; VI-NEXT: v_mov_b32_e32 v3, s2200; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0201; VI-NEXT: s_endpgm202;203; EG-LABEL: test_select_v4i32:204; EG: ; %bb.0: ; %entry205; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]206; EG-NEXT: TEX 1 @6207; EG-NEXT: ALU 9, @12, KC0[CB0:0-32], KC1[]208; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1209; EG-NEXT: CF_END210; EG-NEXT: PAD211; EG-NEXT: Fetch clause starting at 6:212; EG-NEXT: VTX_READ_128 T1.XYZW, T1.X, 0, #1213; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1214; EG-NEXT: ALU clause starting at 10:215; EG-NEXT: MOV T0.X, KC0[2].Z,216; EG-NEXT: MOV * T1.X, KC0[2].W,217; EG-NEXT: ALU clause starting at 12:218; EG-NEXT: SETGT_INT T1.W, T0.W, T1.W,219; EG-NEXT: SETGT_INT * T2.W, T0.Z, T1.Z,220; EG-NEXT: CNDE_INT * T0.W, PV.W, T0.W, KC0[4].X,221; EG-NEXT: CNDE_INT T0.Z, T2.W, T0.Z, KC0[3].W,222; EG-NEXT: SETGT_INT * T1.W, T0.Y, T1.Y,223; EG-NEXT: CNDE_INT T0.Y, PV.W, T0.Y, KC0[3].Z,224; EG-NEXT: SETGT_INT * T1.W, T0.X, T1.X,225; EG-NEXT: CNDE_INT T0.X, PV.W, T0.X, KC0[3].Y,226; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,227; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)228entry:229 %load0 = load <4 x i32>, ptr addrspace(1) %in0230 %load1 = load <4 x i32>, ptr addrspace(1) %in1231 %cmp = icmp sgt <4 x i32> %load0, %load1232 %result = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %load0233 store <4 x i32> %result, ptr addrspace(1) %out234 ret void235}236 237define amdgpu_kernel void @test_select_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {238; SI-LABEL: test_select_v4f32:239; SI: ; %bb.0: ; %entry240; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9241; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd242; SI-NEXT: s_waitcnt lgkmcnt(0)243; SI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0244; SI-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x0245; SI-NEXT: s_mov_b32 s3, 0xf000246; SI-NEXT: s_mov_b32 s2, -1247; SI-NEXT: s_waitcnt lgkmcnt(0)248; SI-NEXT: v_mov_b32_e32 v0, s8249; SI-NEXT: v_mov_b32_e32 v1, s9250; SI-NEXT: v_mov_b32_e32 v2, s10251; SI-NEXT: v_mov_b32_e32 v3, s11252; SI-NEXT: v_mov_b32_e32 v4, s7253; SI-NEXT: v_cmp_neq_f32_e32 vcc, s7, v3254; SI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc255; SI-NEXT: v_mov_b32_e32 v4, s6256; SI-NEXT: v_cmp_neq_f32_e32 vcc, s6, v2257; SI-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc258; SI-NEXT: v_mov_b32_e32 v4, s5259; SI-NEXT: v_cmp_neq_f32_e32 vcc, s5, v1260; SI-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc261; SI-NEXT: v_mov_b32_e32 v4, s4262; SI-NEXT: v_cmp_neq_f32_e32 vcc, s4, v0263; SI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc264; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0265; SI-NEXT: s_endpgm266;267; VI-LABEL: test_select_v4f32:268; VI: ; %bb.0: ; %entry269; VI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x34270; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24271; VI-NEXT: s_mov_b32 s7, 0xf000272; VI-NEXT: s_mov_b32 s6, -1273; VI-NEXT: s_waitcnt lgkmcnt(0)274; VI-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x0275; VI-NEXT: s_mov_b32 s4, s0276; VI-NEXT: s_mov_b32 s5, s1277; VI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0278; VI-NEXT: s_waitcnt lgkmcnt(0)279; VI-NEXT: v_mov_b32_e32 v3, s11280; VI-NEXT: v_mov_b32_e32 v2, s10281; VI-NEXT: v_mov_b32_e32 v1, s9282; VI-NEXT: v_mov_b32_e32 v4, s3283; VI-NEXT: v_cmp_neq_f32_e32 vcc, s3, v3284; VI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc285; VI-NEXT: v_mov_b32_e32 v4, s2286; VI-NEXT: v_cmp_neq_f32_e32 vcc, s2, v2287; VI-NEXT: v_mov_b32_e32 v0, s8288; VI-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc289; VI-NEXT: v_mov_b32_e32 v4, s1290; VI-NEXT: v_cmp_neq_f32_e32 vcc, s1, v1291; VI-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc292; VI-NEXT: v_mov_b32_e32 v4, s0293; VI-NEXT: v_cmp_neq_f32_e32 vcc, s0, v0294; VI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc295; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0296; VI-NEXT: s_endpgm297;298; EG-LABEL: test_select_v4f32:299; EG: ; %bb.0: ; %entry300; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]301; EG-NEXT: TEX 1 @6302; EG-NEXT: ALU 9, @12, KC0[CB0:0-32], KC1[]303; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1304; EG-NEXT: CF_END305; EG-NEXT: PAD306; EG-NEXT: Fetch clause starting at 6:307; EG-NEXT: VTX_READ_128 T1.XYZW, T1.X, 0, #1308; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1309; EG-NEXT: ALU clause starting at 10:310; EG-NEXT: MOV T0.X, KC0[2].Z,311; EG-NEXT: MOV * T1.X, KC0[2].W,312; EG-NEXT: ALU clause starting at 12:313; EG-NEXT: SETNE_DX10 T2.W, T0.W, T1.W,314; EG-NEXT: SETNE_DX10 * T3.W, T0.Z, T1.Z,315; EG-NEXT: CNDE_INT * T0.W, PV.W, T1.W, T0.W,316; EG-NEXT: CNDE_INT T0.Z, T3.W, T1.Z, T0.Z,317; EG-NEXT: SETNE_DX10 * T1.W, T0.Y, T1.Y,318; EG-NEXT: CNDE_INT T0.Y, PV.W, T1.Y, T0.Y,319; EG-NEXT: SETNE_DX10 * T1.W, T0.X, T1.X,320; EG-NEXT: CNDE_INT T0.X, PV.W, T1.X, T0.X,321; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,322; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)323entry:324 %0 = load <4 x float>, ptr addrspace(1) %in0325 %1 = load <4 x float>, ptr addrspace(1) %in1326 %cmp = fcmp une <4 x float> %0, %1327 %result = select <4 x i1> %cmp, <4 x float> %0, <4 x float> %1328 store <4 x float> %result, ptr addrspace(1) %out329 ret void330}331