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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx950 < %s | FileCheck %s3 4declare void @llvm.amdgcn.sched.barrier(i32 %mask)5declare void @llvm.amdgcn.load.to.lds(ptr %in, ptr addrspace(3) %lds_out, i32 %size, i32 %offset, i32 %aux)6 7define amdgpu_kernel void @test_waitcnt(ptr addrspace(1) %global_buffer, ptr addrspace(3) %lds_buffer1, ptr addrspace(3) %lds_buffer2) #0 {8; This test checks if SIInsertWaitcnts pass inserts S_WAITCNT VMCNT(0) before DS_READ9; CHECK-LABEL: test_waitcnt:10; CHECK: ; %bb.0: ; %entry11; CHECK-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x012; CHECK-NEXT: v_mov_b32_e32 v0, 013; CHECK-NEXT: s_waitcnt lgkmcnt(0)14; CHECK-NEXT: s_add_u32 s4, s0, 6415; CHECK-NEXT: s_addc_u32 s5, s1, 016; CHECK-NEXT: s_mov_b32 m0, s217; CHECK-NEXT: s_nop 018; CHECK-NEXT: global_load_lds_dword v0, s[4:5] offset:419; CHECK-NEXT: s_load_dword s4, s[0:1], 0x020; CHECK-NEXT: s_waitcnt lgkmcnt(0)21; CHECK-NEXT: v_mov_b32_e32 v3, s422; CHECK-NEXT: global_store_dword v0, v3, s[0:1] offset:6423; CHECK-NEXT: ; sched_barrier mask(0x00000000)24; CHECK-NEXT: v_mov_b32_e32 v1, s225; CHECK-NEXT: v_mov_b32_e32 v2, s326; CHECK-NEXT: ds_write_b32 v1, v327; CHECK-NEXT: ds_write_b32 v2, v328; CHECK-NEXT: ; sched_barrier mask(0x00000000)29; CHECK-NEXT: ds_read_b32 v1, v130; CHECK-NEXT: s_waitcnt lgkmcnt(0)31; CHECK-NEXT: global_store_dword v0, v1, s[0:1] offset:1632; CHECK-NEXT: global_store_dword v0, v3, s[0:1] offset:3233; CHECK-NEXT: s_endpgm34entry:35 ; VMEM accesses with alias.scope36 %vmem_load = load i32, ptr addrspace(1) %global_buffer37 %gepvmem = getelementptr i32, ptr addrspace(1) %global_buffer, i32 1638 store i32 %vmem_load, ptr addrspace(1) %gepvmem, align 4, !alias.scope !039 40 ; Global to LDS load41 %gepvmem.ascast = addrspacecast ptr addrspace(1) %gepvmem to ptr42 call void @llvm.amdgcn.load.to.lds(ptr %gepvmem.ascast, ptr addrspace(3) %lds_buffer1, i32 4, i32 4, i32 0), !alias.scope !9, !noalias !1443 44 ; Insert scheduling barrier45 call void @llvm.amdgcn.sched.barrier(i32 0)46 47 ; DS_WRITEs with alias.scope and noalias48 store i32 %vmem_load, ptr addrspace(3) %lds_buffer1, align 4, !alias.scope !1, !noalias !1249 store i32 %vmem_load, ptr addrspace(3) %lds_buffer2, align 4, !alias.scope !6, !noalias !1350 51 ; Insert scheduling barrier52 call void @llvm.amdgcn.sched.barrier(i32 0)53 54 ; DS_READ with alias.scope missing55 %lds_load = load i32, ptr addrspace(3) %lds_buffer1, align 4, !noalias !1256 57 ; VMEM write58 %gep = getelementptr i32, ptr addrspace(1) %global_buffer, i32 459 %gep2 = getelementptr i32, ptr addrspace(1) %global_buffer, i32 860 store i32 %lds_load, ptr addrspace(1) %gep, align 4, !alias.scope !061 store i32 %vmem_load, ptr addrspace(1) %gep2, align 4, !alias.scope !062 63 ret void64}65 66; VMEM alias domain and scope67!5 = !{!"vmem.domain"}68!4 = !{!"vmem.scope", !5}69!0 = !{!4}70 71; LDS alias domains and scopes72!3 = !{!"lds1.domain"}73!2 = !{!"lds1.scope", !3}74!1 = !{!2}75 76!8 = !{!"lds2.domain"}77!7 = !{!"lds2.scope", !8}78!6 = !{!7}79 80!11 = !{!"lds1_off4.domain"}81!10 = !{!"lds1_off4.scope", !11}82!9 = !{!10}83 84; Noalias lists85!12 = !{!7, !10}86!13 = !{!2, !10}87!14 = !{!2, !7}88 89attributes #0 = { nounwind }90