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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=gfx802 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,GFX8 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,GFX9 %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=-back-off-barrier -asm-verbose=0 < %s | FileCheck -check-prefix=GCN %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-back-off-barrier -asm-verbose=0 < %s | FileCheck -check-prefix=GCN %s6 7define amdgpu_kernel void @barrier_vmcnt_global(ptr addrspace(1) %arg) {8; GFX8-LABEL: barrier_vmcnt_global:9; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x2410; GFX8-NEXT: v_lshlrev_b32_e32 v1, 2, v011; GFX8-NEXT: s_waitcnt lgkmcnt(0)12; GFX8-NEXT: v_mov_b32_e32 v3, s113; GFX8-NEXT: v_add_u32_e32 v1, vcc, s0, v114; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc15; GFX8-NEXT: flat_load_dword v4, v[1:2]16; GFX8-NEXT: v_mov_b32_e32 v1, 017; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v018; GFX8-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2]19; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v020; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc21; GFX8-NEXT: s_waitcnt vmcnt(0)22; GFX8-NEXT: s_barrier23; GFX8-NEXT: flat_store_dword v[0:1], v424; GFX8-NEXT: s_endpgm25;26; GFX9-LABEL: barrier_vmcnt_global:27; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x2428; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v029; GFX9-NEXT: s_waitcnt lgkmcnt(0)30; GFX9-NEXT: global_load_dword v2, v1, s[0:1]31; GFX9-NEXT: v_add_u32_e32 v1, 1, v032; GFX9-NEXT: v_mov_b32_e32 v0, 033; GFX9-NEXT: v_lshrrev_b64 v[0:1], 30, v[0:1]34; GFX9-NEXT: v_mov_b32_e32 v3, s135; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v036; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc37; GFX9-NEXT: s_waitcnt vmcnt(0)38; GFX9-NEXT: s_barrier39; GFX9-NEXT: global_store_dword v[0:1], v2, off40; GFX9-NEXT: s_endpgm41bb:42 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()43 %tmp1 = zext i32 %tmp to i6444 %tmp2 = shl nuw nsw i64 %tmp1, 3245 %tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp146 %tmp4 = load i32, ptr addrspace(1) %tmp3, align 447 fence syncscope("singlethread") release48 tail call void @llvm.amdgcn.s.barrier()49 fence syncscope("singlethread") acquire50 %tmp5 = add nuw nsw i64 %tmp2, 429496729651 %tmp6 = lshr exact i64 %tmp5, 3252 %tmp7 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp653 store i32 %tmp4, ptr addrspace(1) %tmp7, align 454 ret void55}56 57define amdgpu_kernel void @barrier_vscnt_global(ptr addrspace(1) %arg) {58; GFX8-LABEL: barrier_vscnt_global:59; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x2460; GFX8-NEXT: v_add_u32_e32 v2, vcc, 2, v061; GFX8-NEXT: v_mov_b32_e32 v1, 062; GFX8-NEXT: v_lshrrev_b64 v[2:3], 30, v[1:2]63; GFX8-NEXT: s_waitcnt lgkmcnt(0)64; GFX8-NEXT: v_mov_b32_e32 v4, s165; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v266; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc67; GFX8-NEXT: flat_store_dword v[2:3], v168; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v069; GFX8-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2]70; GFX8-NEXT: v_mov_b32_e32 v3, 171; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v072; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc73; GFX8-NEXT: s_waitcnt vmcnt(0)74; GFX8-NEXT: s_barrier75; GFX8-NEXT: flat_store_dword v[0:1], v376; GFX8-NEXT: s_endpgm77;78; GFX9-LABEL: barrier_vscnt_global:79; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x2480; GFX9-NEXT: v_mov_b32_e32 v1, 081; GFX9-NEXT: v_add_u32_e32 v2, 2, v082; GFX9-NEXT: v_lshrrev_b64 v[2:3], 30, v[1:2]83; GFX9-NEXT: s_waitcnt lgkmcnt(0)84; GFX9-NEXT: v_mov_b32_e32 v4, s185; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v286; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v3, vcc87; GFX9-NEXT: global_store_dword v[2:3], v1, off88; GFX9-NEXT: v_add_u32_e32 v2, 1, v089; GFX9-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2]90; GFX9-NEXT: v_mov_b32_e32 v3, 191; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v092; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v4, v1, vcc93; GFX9-NEXT: s_waitcnt vmcnt(0)94; GFX9-NEXT: s_barrier95; GFX9-NEXT: global_store_dword v[0:1], v3, off96; GFX9-NEXT: s_endpgm97bb:98 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()99 %tmp1 = zext i32 %tmp to i64100 %tmp2 = shl nuw nsw i64 %tmp1, 32101 %tmp3 = add nuw nsw i64 %tmp2, 8589934592102 %tmp4 = lshr exact i64 %tmp3, 32103 %tmp5 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp4104 store i32 0, ptr addrspace(1) %tmp5, align 4105 fence syncscope("singlethread") release106 tail call void @llvm.amdgcn.s.barrier()107 fence syncscope("singlethread") acquire108 %tmp6 = add nuw nsw i64 %tmp2, 4294967296109 %tmp7 = lshr exact i64 %tmp6, 32110 %tmp8 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp7111 store i32 1, ptr addrspace(1) %tmp8, align 4112 ret void113}114 115define amdgpu_kernel void @barrier_vmcnt_vscnt_global(ptr addrspace(1) %arg) {116; GFX8-LABEL: barrier_vmcnt_vscnt_global:117; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x24118; GFX8-NEXT: v_add_u32_e32 v2, vcc, 2, v0119; GFX8-NEXT: v_mov_b32_e32 v1, 0120; GFX8-NEXT: v_lshrrev_b64 v[2:3], 30, v[1:2]121; GFX8-NEXT: s_waitcnt lgkmcnt(0)122; GFX8-NEXT: v_mov_b32_e32 v4, s1123; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v2124; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc125; GFX8-NEXT: flat_store_dword v[2:3], v1126; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0127; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v2128; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc129; GFX8-NEXT: flat_load_dword v3, v[2:3]130; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v0131; GFX8-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2]132; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0133; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc134; GFX8-NEXT: s_waitcnt vmcnt(0)135; GFX8-NEXT: s_barrier136; GFX8-NEXT: flat_store_dword v[0:1], v3137; GFX8-NEXT: s_endpgm138;139; GFX9-LABEL: barrier_vmcnt_vscnt_global:140; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24141; GFX9-NEXT: v_mov_b32_e32 v1, 0142; GFX9-NEXT: v_add_u32_e32 v2, 2, v0143; GFX9-NEXT: v_lshrrev_b64 v[2:3], 30, v[1:2]144; GFX9-NEXT: s_waitcnt lgkmcnt(0)145; GFX9-NEXT: v_mov_b32_e32 v4, s1146; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2147; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v3, vcc148; GFX9-NEXT: global_store_dword v[2:3], v1, off149; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0150; GFX9-NEXT: global_load_dword v3, v2, s[0:1]151; GFX9-NEXT: v_add_u32_e32 v2, 1, v0152; GFX9-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2]153; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0154; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v4, v1, vcc155; GFX9-NEXT: s_waitcnt vmcnt(0)156; GFX9-NEXT: s_barrier157; GFX9-NEXT: global_store_dword v[0:1], v3, off158; GFX9-NEXT: s_endpgm159bb:160 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()161 %tmp1 = zext i32 %tmp to i64162 %tmp2 = shl nuw nsw i64 %tmp1, 32163 %tmp3 = add nuw nsw i64 %tmp2, 8589934592164 %tmp4 = lshr exact i64 %tmp3, 32165 %tmp5 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp4166 store i32 0, ptr addrspace(1) %tmp5, align 4167 %tmp6 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp1168 %tmp7 = load i32, ptr addrspace(1) %tmp6, align 4169 fence syncscope("singlethread") release170 tail call void @llvm.amdgcn.s.barrier()171 fence syncscope("singlethread") acquire172 %tmp8 = add nuw nsw i64 %tmp2, 4294967296173 %tmp9 = lshr exact i64 %tmp8, 32174 %tmp10 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp9175 store i32 %tmp7, ptr addrspace(1) %tmp10, align 4176 ret void177}178 179define amdgpu_kernel void @barrier_vmcnt_flat(ptr %arg) {180; GFX8-LABEL: barrier_vmcnt_flat:181; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x24182; GFX8-NEXT: v_lshlrev_b32_e32 v1, 2, v0183; GFX8-NEXT: s_waitcnt lgkmcnt(0)184; GFX8-NEXT: v_mov_b32_e32 v3, s1185; GFX8-NEXT: v_add_u32_e32 v1, vcc, s0, v1186; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc187; GFX8-NEXT: flat_load_dword v4, v[1:2]188; GFX8-NEXT: v_mov_b32_e32 v1, 0189; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v0190; GFX8-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2]191; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0192; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc193; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)194; GFX8-NEXT: s_barrier195; GFX8-NEXT: flat_store_dword v[0:1], v4196; GFX8-NEXT: s_endpgm197;198; GFX9-LABEL: barrier_vmcnt_flat:199; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24200; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0201; GFX9-NEXT: s_waitcnt lgkmcnt(0)202; GFX9-NEXT: v_mov_b32_e32 v3, s1203; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s0, v1204; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v3, vcc205; GFX9-NEXT: flat_load_dword v4, v[1:2]206; GFX9-NEXT: v_mov_b32_e32 v1, 0207; GFX9-NEXT: v_add_u32_e32 v2, 1, v0208; GFX9-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2]209; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0210; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc211; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)212; GFX9-NEXT: s_barrier213; GFX9-NEXT: flat_store_dword v[0:1], v4214; GFX9-NEXT: s_endpgm215bb:216 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()217 %tmp1 = zext i32 %tmp to i64218 %tmp2 = shl nuw nsw i64 %tmp1, 32219 %tmp3 = getelementptr inbounds i32, ptr %arg, i64 %tmp1220 %tmp4 = load i32, ptr %tmp3, align 4221 fence syncscope("singlethread") release222 tail call void @llvm.amdgcn.s.barrier()223 fence syncscope("singlethread") acquire224 %tmp5 = add nuw nsw i64 %tmp2, 4294967296225 %tmp6 = lshr exact i64 %tmp5, 32226 %tmp7 = getelementptr inbounds i32, ptr %arg, i64 %tmp6227 store i32 %tmp4, ptr %tmp7, align 4228 ret void229}230 231define amdgpu_kernel void @barrier_vscnt_flat(ptr %arg) {232; GFX8-LABEL: barrier_vscnt_flat:233; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x24234; GFX8-NEXT: v_add_u32_e32 v2, vcc, 2, v0235; GFX8-NEXT: v_mov_b32_e32 v1, 0236; GFX8-NEXT: v_lshrrev_b64 v[2:3], 30, v[1:2]237; GFX8-NEXT: s_waitcnt lgkmcnt(0)238; GFX8-NEXT: v_mov_b32_e32 v4, s1239; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v2240; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc241; GFX8-NEXT: flat_store_dword v[2:3], v1242; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v0243; GFX8-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2]244; GFX8-NEXT: v_mov_b32_e32 v3, 1245; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0246; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc247; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)248; GFX8-NEXT: s_barrier249; GFX8-NEXT: flat_store_dword v[0:1], v3250; GFX8-NEXT: s_endpgm251;252; GFX9-LABEL: barrier_vscnt_flat:253; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24254; GFX9-NEXT: v_mov_b32_e32 v1, 0255; GFX9-NEXT: v_add_u32_e32 v2, 2, v0256; GFX9-NEXT: v_lshrrev_b64 v[2:3], 30, v[1:2]257; GFX9-NEXT: s_waitcnt lgkmcnt(0)258; GFX9-NEXT: v_mov_b32_e32 v4, s1259; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2260; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v3, vcc261; GFX9-NEXT: flat_store_dword v[2:3], v1262; GFX9-NEXT: v_add_u32_e32 v2, 1, v0263; GFX9-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2]264; GFX9-NEXT: v_mov_b32_e32 v3, 1265; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0266; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v4, v1, vcc267; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)268; GFX9-NEXT: s_barrier269; GFX9-NEXT: flat_store_dword v[0:1], v3270; GFX9-NEXT: s_endpgm271bb:272 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()273 %tmp1 = zext i32 %tmp to i64274 %tmp2 = shl nuw nsw i64 %tmp1, 32275 %tmp3 = add nuw nsw i64 %tmp2, 8589934592276 %tmp4 = lshr exact i64 %tmp3, 32277 %tmp5 = getelementptr inbounds i32, ptr %arg, i64 %tmp4278 store i32 0, ptr %tmp5, align 4279 fence syncscope("singlethread") release280 tail call void @llvm.amdgcn.s.barrier()281 fence syncscope("singlethread") acquire282 %tmp6 = add nuw nsw i64 %tmp2, 4294967296283 %tmp7 = lshr exact i64 %tmp6, 32284 %tmp8 = getelementptr inbounds i32, ptr %arg, i64 %tmp7285 store i32 1, ptr %tmp8, align 4286 ret void287}288 289define amdgpu_kernel void @barrier_vmcnt_vscnt_flat(ptr %arg) {290; GFX8-LABEL: barrier_vmcnt_vscnt_flat:291; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x24292; GFX8-NEXT: v_add_u32_e32 v2, vcc, 2, v0293; GFX8-NEXT: v_mov_b32_e32 v1, 0294; GFX8-NEXT: v_lshrrev_b64 v[2:3], 30, v[1:2]295; GFX8-NEXT: s_waitcnt lgkmcnt(0)296; GFX8-NEXT: v_mov_b32_e32 v4, s1297; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v2298; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc299; GFX8-NEXT: flat_store_dword v[2:3], v1300; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0301; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v2302; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc303; GFX8-NEXT: flat_load_dword v3, v[2:3]304; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v0305; GFX8-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2]306; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0307; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc308; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)309; GFX8-NEXT: s_barrier310; GFX8-NEXT: flat_store_dword v[0:1], v3311; GFX8-NEXT: s_endpgm312;313; GFX9-LABEL: barrier_vmcnt_vscnt_flat:314; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24315; GFX9-NEXT: v_mov_b32_e32 v1, 0316; GFX9-NEXT: v_add_u32_e32 v2, 2, v0317; GFX9-NEXT: v_lshrrev_b64 v[2:3], 30, v[1:2]318; GFX9-NEXT: s_waitcnt lgkmcnt(0)319; GFX9-NEXT: v_mov_b32_e32 v4, s1320; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2321; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v3, vcc322; GFX9-NEXT: flat_store_dword v[2:3], v1323; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0324; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2325; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc326; GFX9-NEXT: flat_load_dword v3, v[2:3]327; GFX9-NEXT: v_add_u32_e32 v2, 1, v0328; GFX9-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2]329; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0330; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v4, v1, vcc331; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)332; GFX9-NEXT: s_barrier333; GFX9-NEXT: flat_store_dword v[0:1], v3334; GFX9-NEXT: s_endpgm335bb:336 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()337 %tmp1 = zext i32 %tmp to i64338 %tmp2 = shl nuw nsw i64 %tmp1, 32339 %tmp3 = add nuw nsw i64 %tmp2, 8589934592340 %tmp4 = lshr exact i64 %tmp3, 32341 %tmp5 = getelementptr inbounds i32, ptr %arg, i64 %tmp4342 store i32 0, ptr %tmp5, align 4343 %tmp6 = getelementptr inbounds i32, ptr %arg, i64 %tmp1344 %tmp7 = load i32, ptr %tmp6, align 4345 fence syncscope("singlethread") release346 tail call void @llvm.amdgcn.s.barrier()347 fence syncscope("singlethread") acquire348 %tmp8 = add nuw nsw i64 %tmp2, 4294967296349 %tmp9 = lshr exact i64 %tmp8, 32350 %tmp10 = getelementptr inbounds i32, ptr %arg, i64 %tmp9351 store i32 %tmp7, ptr %tmp10, align 4352 ret void353}354 355define amdgpu_kernel void @barrier_vmcnt_vscnt_flat_workgroup(ptr %arg) {356; GFX8-LABEL: barrier_vmcnt_vscnt_flat_workgroup:357; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x24358; GFX8-NEXT: v_add_u32_e32 v2, vcc, 2, v0359; GFX8-NEXT: v_mov_b32_e32 v1, 0360; GFX8-NEXT: v_lshrrev_b64 v[2:3], 30, v[1:2]361; GFX8-NEXT: s_waitcnt lgkmcnt(0)362; GFX8-NEXT: v_mov_b32_e32 v4, s1363; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v2364; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc365; GFX8-NEXT: flat_store_dword v[2:3], v1366; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0367; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v2368; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc369; GFX8-NEXT: flat_load_dword v3, v[2:3]370; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v0371; GFX8-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2]372; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0373; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc374; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)375; GFX8-NEXT: s_barrier376; GFX8-NEXT: flat_store_dword v[0:1], v3377; GFX8-NEXT: s_endpgm378;379; GFX9-LABEL: barrier_vmcnt_vscnt_flat_workgroup:380; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24381; GFX9-NEXT: v_mov_b32_e32 v1, 0382; GFX9-NEXT: v_add_u32_e32 v2, 2, v0383; GFX9-NEXT: v_lshrrev_b64 v[2:3], 30, v[1:2]384; GFX9-NEXT: s_waitcnt lgkmcnt(0)385; GFX9-NEXT: v_mov_b32_e32 v4, s1386; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2387; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v3, vcc388; GFX9-NEXT: flat_store_dword v[2:3], v1389; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0390; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2391; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc392; GFX9-NEXT: flat_load_dword v3, v[2:3]393; GFX9-NEXT: v_add_u32_e32 v2, 1, v0394; GFX9-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2]395; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0396; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v4, v1, vcc397; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)398; GFX9-NEXT: s_barrier399; GFX9-NEXT: flat_store_dword v[0:1], v3400; GFX9-NEXT: s_endpgm401bb:402 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()403 %tmp1 = zext i32 %tmp to i64404 %tmp2 = shl nuw nsw i64 %tmp1, 32405 %tmp3 = add nuw nsw i64 %tmp2, 8589934592406 %tmp4 = lshr exact i64 %tmp3, 32407 %tmp5 = getelementptr inbounds i32, ptr %arg, i64 %tmp4408 store i32 0, ptr %tmp5, align 4409 %tmp6 = getelementptr inbounds i32, ptr %arg, i64 %tmp1410 %tmp7 = load i32, ptr %tmp6, align 4411 fence syncscope("workgroup") release412 tail call void @llvm.amdgcn.s.barrier()413 fence syncscope("workgroup") acquire414 %tmp8 = add nuw nsw i64 %tmp2, 4294967296415 %tmp9 = lshr exact i64 %tmp8, 32416 %tmp10 = getelementptr inbounds i32, ptr %arg, i64 %tmp9417 store i32 %tmp7, ptr %tmp10, align 4418 ret void419}420 421define amdgpu_kernel void @load_vmcnt_global(ptr addrspace(1) %arg) {422; GFX8-LABEL: load_vmcnt_global:423; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x24424; GFX8-NEXT: v_lshlrev_b32_e32 v1, 2, v0425; GFX8-NEXT: s_waitcnt lgkmcnt(0)426; GFX8-NEXT: v_mov_b32_e32 v3, s1427; GFX8-NEXT: v_add_u32_e32 v1, vcc, s0, v1428; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc429; GFX8-NEXT: flat_load_dword v4, v[1:2]430; GFX8-NEXT: v_mov_b32_e32 v1, 0431; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v0432; GFX8-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2]433; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0434; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc435; GFX8-NEXT: s_waitcnt vmcnt(0)436; GFX8-NEXT: flat_store_dword v[0:1], v4437; GFX8-NEXT: s_endpgm438;439; GFX9-LABEL: load_vmcnt_global:440; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24441; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0442; GFX9-NEXT: s_waitcnt lgkmcnt(0)443; GFX9-NEXT: global_load_dword v2, v1, s[0:1]444; GFX9-NEXT: v_add_u32_e32 v1, 1, v0445; GFX9-NEXT: v_mov_b32_e32 v0, 0446; GFX9-NEXT: v_lshrrev_b64 v[0:1], 30, v[0:1]447; GFX9-NEXT: v_mov_b32_e32 v3, s1448; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0449; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc450; GFX9-NEXT: s_waitcnt vmcnt(0)451; GFX9-NEXT: global_store_dword v[0:1], v2, off452; GFX9-NEXT: s_endpgm453bb:454 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()455 %tmp1 = zext i32 %tmp to i64456 %tmp2 = shl nuw nsw i64 %tmp1, 32457 %tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp1458 %tmp4 = load i32, ptr addrspace(1) %tmp3, align 4459 %tmp5 = add nuw nsw i64 %tmp2, 4294967296460 %tmp6 = lshr exact i64 %tmp5, 32461 %tmp7 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp6462 store i32 %tmp4, ptr addrspace(1) %tmp7, align 4463 ret void464}465 466define amdgpu_kernel void @load_vmcnt_flat(ptr %arg) {467; GFX8-LABEL: load_vmcnt_flat:468; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x24469; GFX8-NEXT: v_lshlrev_b32_e32 v1, 2, v0470; GFX8-NEXT: s_waitcnt lgkmcnt(0)471; GFX8-NEXT: v_mov_b32_e32 v3, s1472; GFX8-NEXT: v_add_u32_e32 v1, vcc, s0, v1473; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc474; GFX8-NEXT: flat_load_dword v4, v[1:2]475; GFX8-NEXT: v_mov_b32_e32 v1, 0476; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v0477; GFX8-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2]478; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0479; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc480; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)481; GFX8-NEXT: flat_store_dword v[0:1], v4482; GFX8-NEXT: s_endpgm483;484; GFX9-LABEL: load_vmcnt_flat:485; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24486; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0487; GFX9-NEXT: s_waitcnt lgkmcnt(0)488; GFX9-NEXT: v_mov_b32_e32 v3, s1489; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s0, v1490; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v3, vcc491; GFX9-NEXT: flat_load_dword v4, v[1:2]492; GFX9-NEXT: v_mov_b32_e32 v1, 0493; GFX9-NEXT: v_add_u32_e32 v2, 1, v0494; GFX9-NEXT: v_lshrrev_b64 v[0:1], 30, v[1:2]495; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0496; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc497; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)498; GFX9-NEXT: flat_store_dword v[0:1], v4499; GFX9-NEXT: s_endpgm500bb:501 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()502 %tmp1 = zext i32 %tmp to i64503 %tmp2 = shl nuw nsw i64 %tmp1, 32504 %tmp3 = getelementptr inbounds i32, ptr %arg, i64 %tmp1505 %tmp4 = load i32, ptr %tmp3, align 4506 %tmp5 = add nuw nsw i64 %tmp2, 4294967296507 %tmp6 = lshr exact i64 %tmp5, 32508 %tmp7 = getelementptr inbounds i32, ptr %arg, i64 %tmp6509 store i32 %tmp4, ptr %tmp7, align 4510 ret void511}512 513define void @store_vscnt_private(ptr addrspace(5) %p) {514; GFX8-LABEL: store_vscnt_private:515; GFX8: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)516; GFX8-NEXT: v_mov_b32_e32 v1, 0517; GFX8-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen518; GFX8-NEXT: s_waitcnt vmcnt(0)519; GFX8-NEXT: s_setpc_b64 s[30:31]520;521; GFX9-LABEL: store_vscnt_private:522; GFX9: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)523; GFX9-NEXT: v_mov_b32_e32 v1, 0524; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen525; GFX9-NEXT: s_waitcnt vmcnt(0)526; GFX9-NEXT: s_setpc_b64 s[30:31]527 store i32 0, ptr addrspace(5) %p528 ret void529}530 531define void @store_vscnt_global(ptr addrspace(1) %p) {532; GFX8-LABEL: store_vscnt_global:533; GFX8: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)534; GFX8-NEXT: v_mov_b32_e32 v2, 0535; GFX8-NEXT: flat_store_dword v[0:1], v2536; GFX8-NEXT: s_waitcnt vmcnt(0)537; GFX8-NEXT: s_setpc_b64 s[30:31]538;539; GFX9-LABEL: store_vscnt_global:540; GFX9: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)541; GFX9-NEXT: v_mov_b32_e32 v2, 0542; GFX9-NEXT: global_store_dword v[0:1], v2, off543; GFX9-NEXT: s_waitcnt vmcnt(0)544; GFX9-NEXT: s_setpc_b64 s[30:31]545 store i32 0, ptr addrspace(1) %p546 ret void547}548 549define void @store_vscnt_flat(ptr %p) {550; GFX8-LABEL: store_vscnt_flat:551; GFX8: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)552; GFX8-NEXT: v_mov_b32_e32 v2, 0553; GFX8-NEXT: flat_store_dword v[0:1], v2554; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)555; GFX8-NEXT: s_setpc_b64 s[30:31]556;557; GFX9-LABEL: store_vscnt_flat:558; GFX9: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)559; GFX9-NEXT: v_mov_b32_e32 v2, 0560; GFX9-NEXT: flat_store_dword v[0:1], v2561; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)562; GFX9-NEXT: s_setpc_b64 s[30:31]563 store i32 0, ptr %p564 ret void565}566 567define void @function_prologue() {568; GCN-LABEL: function_prologue:569; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)570; GCN-NEXT: s_setpc_b64 s[30:31]571 ret void572}573 574declare void @llvm.amdgcn.s.barrier()575declare i32 @llvm.amdgcn.workitem.id.x()576