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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefix=GFX906 %s3declare float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32>, i32, i32, i32 immarg) #04declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg) #15 6; Check that the compiler doesn't crash with a "undefined physical register" error;7; bb.0 sets SCC bit in s_cmp_eq_u32 s0, 18; bb.1 overrides it9; bb.2 uses the value from bb.010; Preserve SCC across bb.1 with s_cselect_b32 s5, 1, 0 -> s_cmp_lg_u32 s5, 011; Otherwise, we will see the following error.12;*** Bad machine code: Using an undefined physical register ***13;- function: foo14;- basic block: %bb.3 (0x53198c0)15;- instruction: %33.sub1:sgpr_128 = S_CSELECT_B32 1072693248, 0, implicit $scc16;- operand 3: implicit $scc17 18define amdgpu_kernel void @foo(i1 %cmp1) {19; GFX906-LABEL: foo:20; GFX906: ; %bb.0: ; %entry21; GFX906-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD022; GFX906-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD123; GFX906-NEXT: s_mov_b32 s14, -124; GFX906-NEXT: s_mov_b32 s15, 0xe0000025; GFX906-NEXT: s_add_u32 s12, s12, s1126; GFX906-NEXT: s_addc_u32 s13, s13, 027; GFX906-NEXT: buffer_load_dword v3, off, s[12:15], 028; GFX906-NEXT: buffer_load_dword v4, off, s[12:15], 0 offset:429; GFX906-NEXT: buffer_load_dword v5, off, s[12:15], 0 offset:830; GFX906-NEXT: buffer_load_dword v6, off, s[12:15], 0 offset:1231; GFX906-NEXT: s_load_dword s2, s[4:5], 0x2432; GFX906-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x1c33; GFX906-NEXT: s_mov_b32 s4, 034; GFX906-NEXT: s_waitcnt lgkmcnt(0)35; GFX906-NEXT: s_bitcmp1_b32 s2, 036; GFX906-NEXT: s_mul_i32 s0, s0, s137; GFX906-NEXT: v_mul_u32_u24_e32 v1, s1, v138; GFX906-NEXT: v_mad_u32_u24 v0, s0, v0, v139; GFX906-NEXT: v_add_lshl_u32 v2, v0, v2, 440; GFX906-NEXT: v_mov_b32_e32 v0, 041; GFX906-NEXT: v_mov_b32_e32 v1, v042; GFX906-NEXT: s_cselect_b32 s5, 1, 043; GFX906-NEXT: s_mov_b64 s[2:3], exec44; GFX906-NEXT: ds_write_b64 v2, v[0:1]45; GFX906-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=146; GFX906-NEXT: s_waitcnt vmcnt(3)47; GFX906-NEXT: v_readfirstlane_b32 s0, v348; GFX906-NEXT: s_waitcnt vmcnt(2)49; GFX906-NEXT: v_readfirstlane_b32 s1, v450; GFX906-NEXT: v_cmp_eq_u64_e32 vcc, s[0:1], v[3:4]51; GFX906-NEXT: s_waitcnt vmcnt(1)52; GFX906-NEXT: v_readfirstlane_b32 s0, v553; GFX906-NEXT: s_waitcnt vmcnt(0)54; GFX906-NEXT: v_readfirstlane_b32 s1, v655; GFX906-NEXT: v_cmp_eq_u64_e64 s[0:1], s[0:1], v[5:6]56; GFX906-NEXT: s_and_b64 s[0:1], vcc, s[0:1]57; GFX906-NEXT: s_and_saveexec_b64 s[0:1], s[0:1]58; GFX906-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr659; GFX906-NEXT: s_xor_b64 exec, exec, s[0:1]60; GFX906-NEXT: s_cbranch_execnz .LBB0_161; GFX906-NEXT: ; %bb.2:62; GFX906-NEXT: s_cmp_lg_u32 s5, 063; GFX906-NEXT: s_mov_b64 exec, s[2:3]64; GFX906-NEXT: s_cselect_b32 s5, 0x3ff00000, 065; GFX906-NEXT: v_cvt_f32_f64_e32 v0, s[4:5]66; GFX906-NEXT: s_mov_b32 s5, s467; GFX906-NEXT: s_mov_b32 s6, s468; GFX906-NEXT: s_mov_b32 s7, s469; GFX906-NEXT: buffer_store_dword v0, off, s[4:7], 070; GFX906-NEXT: s_endpgm71entry:72 %wbr = alloca <4 x i32>, align 16, addrspace(5)73 store ptr null, ptr addrspace(5) %wbr, align 1674 %wbr_1 = load <4 x i32>, ptr addrspace(5) null, align 1675 %call1 = tail call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %wbr_1, i32 0, i32 0, i32 0)76 %0 = fpext float %call1 to double77 %sel1 = select i1 %cmp1, double 1.000000e+00, double 0.000000e+0078 %sel2 = select i1 %cmp1, double %0, double 0.000000e+0079 %mul = fmul double %sel2, 0.000000e+0080 %fptruncate = fptrunc double %sel1 to float81 tail call void @llvm.amdgcn.raw.buffer.store.f32(float %fptruncate, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0)82 ret void83}84