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1; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s2; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s3; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s4; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s5; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s6; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s7 8; This compute shader has input args that claim that it has 17 sgprs and 5 vgprs9; in wave dispatch. Ensure that the sgpr and vgpr counts in COMPUTE_PGM_RSRC110; are set to reflect that, even though the registers are not used in the shader.11 12; GCN-LABEL: {{^}}_amdgpu_cs_main:13; GCN: .amdgpu_pal_metadata14; GCN-NEXT: ---15; GCN-NEXT: amdpal.pipelines:16; GCN-NEXT: - .hardware_stages:17; GCN-NEXT: .cs:18; GCN-NEXT: .entry_point: _amdgpu_cs_main19; GCN-NEXT: .entry_point_symbol: _amdgpu_cs_main20; GCN-NEXT: .scratch_memory_size: 021; SI-NEXT: .sgpr_count: 0x1122; VI-NEXT: .sgpr_count: 0x6023; GFX9-NEXT: .sgpr_count: 0x1524; SI-NEXT: .vgpr_count: 0x525; VI-NEXT: .vgpr_count: 0x526; GFX9-NEXT: .vgpr_count: 0x527; GCN-NEXT: .registers:28; SI-NEXT: '0x2e12 (COMPUTE_PGM_RSRC1)': 0x{{[0-9a-f]*}}8129; VI-NEXT: '0x2e12 (COMPUTE_PGM_RSRC1)': 0x{{[0-9a-f]*}}c130; GFX9-NEXT: '0x2e12 (COMPUTE_PGM_RSRC1)': 0x{{[0-9a-f]*}}8131; GCN-NEXT: '0x2e13 (COMPUTE_PGM_RSRC2)': 032; GCN-NEXT: ...33; GCN-NEXT: .end_amdgpu_pal_metadata34 35define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg, i32 inreg, <2 x i32> inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <5 x i32>) {36.entry:37 ret void38}39