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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefix=GCN3 4define amdgpu_ps float @while_break(i32 %z, float %v, i32 %x, i32 %y) #0 {5; GCN-LABEL: while_break:6; GCN:       ; %bb.0: ; %entry7; GCN-NEXT:    s_mov_b32 s1, -18; GCN-NEXT:    s_mov_b32 s0, 09; GCN-NEXT:    s_branch .LBB0_210; GCN-NEXT:  .LBB0_1: ; %Flow211; GCN-NEXT:    ; in Loop: Header=BB0_2 Depth=112; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s413; GCN-NEXT:    s_and_b32 s2, exec_lo, s314; GCN-NEXT:    s_or_b32 s0, s2, s015; GCN-NEXT:    s_andn2_b32 exec_lo, exec_lo, s016; GCN-NEXT:    s_cbranch_execz .LBB0_817; GCN-NEXT:  .LBB0_2: ; %header18; GCN-NEXT:    ; =>This Inner Loop Header: Depth=119; GCN-NEXT:    s_add_i32 s1, s1, 120; GCN-NEXT:    s_mov_b32 s2, 021; GCN-NEXT:    v_cmp_ge_i32_e32 vcc_lo, s1, v222; GCN-NEXT:    s_and_saveexec_b32 s3, vcc_lo23; GCN-NEXT:    s_xor_b32 s3, exec_lo, s324; GCN-NEXT:  ; %bb.3: ; %else25; GCN-NEXT:    ; in Loop: Header=BB0_2 Depth=126; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, s1, v327; GCN-NEXT:    s_and_b32 s2, vcc_lo, exec_lo28; GCN-NEXT:  ; %bb.4: ; %Flow29; GCN-NEXT:    ; in Loop: Header=BB0_2 Depth=130; GCN-NEXT:    s_andn2_saveexec_b32 s3, s331; GCN-NEXT:  ; %bb.5: ; %if32; GCN-NEXT:    ; in Loop: Header=BB0_2 Depth=133; GCN-NEXT:    v_add_f32_e32 v1, 1.0, v134; GCN-NEXT:    s_or_b32 s2, s2, exec_lo35; GCN-NEXT:  ; %bb.6: ; %Flow136; GCN-NEXT:    ; in Loop: Header=BB0_2 Depth=137; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s338; GCN-NEXT:    s_mov_b32 s3, -139; GCN-NEXT:    s_and_saveexec_b32 s4, s240; GCN-NEXT:    s_cbranch_execz .LBB0_141; GCN-NEXT:  ; %bb.7: ; %latch42; GCN-NEXT:    ; in Loop: Header=BB0_2 Depth=143; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, s1, v044; GCN-NEXT:    s_orn2_b32 s3, vcc_lo, exec_lo45; GCN-NEXT:    s_branch .LBB0_146; GCN-NEXT:  .LBB0_8: ; %end47; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s048; GCN-NEXT:    v_mov_b32_e32 v0, v149; GCN-NEXT:    ; return to shader part epilog50entry:51  br label %header52 53header:54  %v.1 = phi float [ %v, %entry ], [ %v.2, %latch ]55  %ind = phi i32 [ 0, %entry], [ %ind.inc, %latch ]56  %cc = icmp slt i32 %ind, %x57  br i1 %cc, label %if, label %else58 59if:60  %v.if = fadd float %v.1, 1.061  br label %latch62 63else:64  %cc2 = icmp slt i32 %ind, %y65  br i1 %cc2, label %latch, label %end66 67latch:68  %v.2 = phi float [ %v.if, %if ], [ %v.1, %else ]69  %ind.inc = add i32 %ind, 170  %cc3 = icmp slt i32 %ind, %z71  br i1 %cc3, label %end, label %header72 73end:74  %r = phi float [ %v.2, %latch ], [ %v.1, %else ]75  ret float %r76}77 78; Just different dfs order from while_break.79define amdgpu_ps float @while_break2(i32 %z, float %v, i32 %x, i32 %y) #0 {80; GCN-LABEL: while_break2:81; GCN:       ; %bb.0: ; %entry82; GCN-NEXT:    s_mov_b32 s1, -183; GCN-NEXT:    s_mov_b32 s0, 084; GCN-NEXT:    s_branch .LBB1_285; GCN-NEXT:  .LBB1_1: ; %Flow286; GCN-NEXT:    ; in Loop: Header=BB1_2 Depth=187; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s488; GCN-NEXT:    s_and_b32 s2, exec_lo, s389; GCN-NEXT:    s_or_b32 s0, s2, s090; GCN-NEXT:    s_andn2_b32 exec_lo, exec_lo, s091; GCN-NEXT:    s_cbranch_execz .LBB1_892; GCN-NEXT:  .LBB1_2: ; %header93; GCN-NEXT:    ; =>This Inner Loop Header: Depth=194; GCN-NEXT:    s_add_i32 s1, s1, 195; GCN-NEXT:    s_mov_b32 s2, 096; GCN-NEXT:    v_cmp_ge_i32_e32 vcc_lo, s1, v297; GCN-NEXT:    s_and_saveexec_b32 s3, vcc_lo98; GCN-NEXT:    s_xor_b32 s3, exec_lo, s399; GCN-NEXT:  ; %bb.3: ; %if100; GCN-NEXT:    ; in Loop: Header=BB1_2 Depth=1101; GCN-NEXT:    v_add_f32_e32 v1, 1.0, v1102; GCN-NEXT:    s_mov_b32 s2, exec_lo103; GCN-NEXT:  ; %bb.4: ; %Flow104; GCN-NEXT:    ; in Loop: Header=BB1_2 Depth=1105; GCN-NEXT:    s_andn2_saveexec_b32 s3, s3106; GCN-NEXT:  ; %bb.5: ; %else107; GCN-NEXT:    ; in Loop: Header=BB1_2 Depth=1108; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, s1, v3109; GCN-NEXT:    s_andn2_b32 s2, s2, exec_lo110; GCN-NEXT:    s_and_b32 s4, vcc_lo, exec_lo111; GCN-NEXT:    s_or_b32 s2, s2, s4112; GCN-NEXT:  ; %bb.6: ; %Flow1113; GCN-NEXT:    ; in Loop: Header=BB1_2 Depth=1114; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s3115; GCN-NEXT:    s_mov_b32 s3, -1116; GCN-NEXT:    s_and_saveexec_b32 s4, s2117; GCN-NEXT:    s_cbranch_execz .LBB1_1118; GCN-NEXT:  ; %bb.7: ; %latch119; GCN-NEXT:    ; in Loop: Header=BB1_2 Depth=1120; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, s1, v0121; GCN-NEXT:    s_orn2_b32 s3, vcc_lo, exec_lo122; GCN-NEXT:    s_branch .LBB1_1123; GCN-NEXT:  .LBB1_8: ; %end124; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s0125; GCN-NEXT:    v_mov_b32_e32 v0, v1126; GCN-NEXT:    ; return to shader part epilog127entry:128  br label %header129 130header:131  %v.1 = phi float [ %v, %entry ], [ %v.2, %latch ]132  %ind = phi i32 [ 0, %entry], [ %ind.inc, %latch ]133  %cc = icmp slt i32 %ind, %x134  br i1 %cc, label %else, label %if135 136if:137  %v.if = fadd float %v.1, 1.0138  br label %latch139 140else:141  %cc2 = icmp slt i32 %ind, %y142  br i1 %cc2, label %latch, label %end143 144latch:145  %v.2 = phi float [ %v.if, %if ], [ %v.1, %else ]146  %ind.inc = add i32 %ind, 1147  %cc3 = icmp slt i32 %ind, %z148  br i1 %cc3, label %end, label %header149 150end:151  %r = phi float [ %v.2, %latch ], [ %v.1, %else ]152  ret float %r153}154 155; Two chains of phi network that have the same value from %if block.156define amdgpu_ps < 2 x float> @while_break_two_chains_of_phi(float %v, i32 %x, i32 %y, i32 %z, ptr addrspace(1) %p) #0 {157; GCN-LABEL: while_break_two_chains_of_phi:158; GCN:       ; %bb.0: ; %entry159; GCN-NEXT:    v_mov_b32_e32 v6, 0160; GCN-NEXT:    s_mov_b32 s0, 0161; GCN-NEXT:    s_mov_b32 s2, 0162; GCN-NEXT:    s_branch .LBB2_2163; GCN-NEXT:  .LBB2_1: ; %Flow1164; GCN-NEXT:    ; in Loop: Header=BB2_2 Depth=1165; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s4166; GCN-NEXT:    s_and_b32 s1, exec_lo, s1167; GCN-NEXT:    s_or_b32 s2, s1, s2168; GCN-NEXT:    s_andn2_b32 exec_lo, exec_lo, s2169; GCN-NEXT:    s_cbranch_execz .LBB2_6170; GCN-NEXT:  .LBB2_2: ; %header171; GCN-NEXT:    ; =>This Inner Loop Header: Depth=1172; GCN-NEXT:    v_cmp_ge_i32_e64 s3, s0, v1173; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, s0, v1174; GCN-NEXT:    s_and_saveexec_b32 s4, vcc_lo175; GCN-NEXT:    s_cbranch_execz .LBB2_4176; GCN-NEXT:  ; %bb.3: ; %if177; GCN-NEXT:    ; in Loop: Header=BB2_2 Depth=1178; GCN-NEXT:    s_ashr_i32 s1, s0, 31179; GCN-NEXT:    s_lshl_b64 s[6:7], s[0:1], 2180; GCN-NEXT:    s_andn2_b32 s1, s3, exec_lo181; GCN-NEXT:    v_add_co_u32 v6, vcc_lo, v4, s6182; GCN-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo183; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, s0, v2184; GCN-NEXT:    global_load_dword v0, v[6:7], off185; GCN-NEXT:    s_and_b32 s3, vcc_lo, exec_lo186; GCN-NEXT:    s_or_b32 s3, s1, s3187; GCN-NEXT:    s_waitcnt vmcnt(0)188; GCN-NEXT:    v_add_f32_e32 v6, 1.0, v0189; GCN-NEXT:    v_mov_b32_e32 v0, v6190; GCN-NEXT:  .LBB2_4: ; %Flow191; GCN-NEXT:    ; in Loop: Header=BB2_2 Depth=1192; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s4193; GCN-NEXT:    s_mov_b32 s1, -1194; GCN-NEXT:    s_and_saveexec_b32 s4, s3195; GCN-NEXT:    s_cbranch_execz .LBB2_1196; GCN-NEXT:  ; %bb.5: ; %latch197; GCN-NEXT:    ; in Loop: Header=BB2_2 Depth=1198; GCN-NEXT:    v_cmp_lt_i32_e32 vcc_lo, s0, v3199; GCN-NEXT:    s_add_i32 s0, s0, 1200; GCN-NEXT:    s_orn2_b32 s1, vcc_lo, exec_lo201; GCN-NEXT:    s_branch .LBB2_1202; GCN-NEXT:  .LBB2_6: ; %end203; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s2204; GCN-NEXT:    v_mov_b32_e32 v1, v6205; GCN-NEXT:    ; return to shader part epilog206entry:207  br label %header208 209header:210  %v.1 = phi float [ %v, %entry ], [ %v.2, %latch ]211  %v.copy = phi float [ 0.0, %entry ], [ %v.copy.2, %latch ]212  %ind = phi i32 [ 0, %entry], [ %ind.inc, %latch ]213  %cc = icmp slt i32 %ind, %x214  br i1 %cc, label %if, label %latch215 216if:217  %v.ptr = getelementptr float, ptr addrspace(1) %p, i32 %ind218  %v.load = load float, ptr addrspace(1) %v.ptr219  %v.if = fadd float %v.load, 1.0220  %cc2 = icmp slt i32 %ind, %y221  br i1 %cc2, label %latch, label %end222 223latch:224  %v.2 = phi float [ %v.1, %header ], [ %v.if, %if ]225  %v.copy.2 = phi float [ %v.copy, %header ], [ %v.if, %if ]226  %ind.inc = add i32 %ind, 1227  %cc3 = icmp slt i32 %ind, %z228  br i1 %cc3, label %end, label %header229 230end:231  %r = phi float [ %v.2, %latch ], [ %v.if, %if ]232  %r2 = phi float [ %v.copy.2, %latch ], [ %v.if, %if ]233  %packed0 = insertelement < 2 x float > poison, float %r, i32 0234  %packed1 = insertelement < 2 x float > %packed0, float %r2, i32 1235  ret < 2 x float> %packed1236}237 238attributes #0 = { nounwind }239