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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefix=GFX90A %s3 4; The test forces a high vector register pressure and there won't be sufficient VGPRs to be allocated5; for writelane/readlane SGPR spill instructions. Regalloc would split the vector register liverange6; by introducing a copy to AGPR register. The VGPR store to AGPR (v_accvgpr_write_b32) and later the7; restore from AGPR (v_accvgpr_read_b32) should be whole-wave operations and hence exec mask should be8; manipulated to ensure all lanes are active when these instructions are executed.9define void @vector_reg_liverange_split() #0 {10; GFX90A-LABEL: vector_reg_liverange_split:11; GFX90A: ; %bb.0:12; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; GFX90A-NEXT: s_mov_b32 s16, s3314; GFX90A-NEXT: s_mov_b32 s33, s3215; GFX90A-NEXT: s_xor_saveexec_b64 s[18:19], -116; GFX90A-NEXT: buffer_store_dword v39, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill17; GFX90A-NEXT: s_mov_b64 exec, -118; GFX90A-NEXT: buffer_store_dword a32, off, s[0:3], s33 ; 4-byte Folded Spill19; GFX90A-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill20; GFX90A-NEXT: s_mov_b64 exec, s[18:19]21; GFX90A-NEXT: v_writelane_b32 v40, s16, 422; GFX90A-NEXT: v_writelane_b32 v40, s28, 223; GFX90A-NEXT: v_writelane_b32 v40, s29, 324; GFX90A-NEXT: v_writelane_b32 v40, s30, 025; GFX90A-NEXT: ; implicit-def: $vgpr39 : SGPR spill to VGPR lane26; GFX90A-NEXT: s_addk_i32 s32, 0x40027; GFX90A-NEXT: v_writelane_b32 v40, s31, 128; GFX90A-NEXT: ;;#ASMSTART29; GFX90A-NEXT: ; def s2030; GFX90A-NEXT: ;;#ASMEND31; GFX90A-NEXT: v_writelane_b32 v39, s20, 032; GFX90A-NEXT: s_or_saveexec_b64 s[28:29], -133; GFX90A-NEXT: v_accvgpr_write_b32 a32, v3934; GFX90A-NEXT: s_mov_b64 exec, s[28:29]35; GFX90A-NEXT: s_getpc_b64 s[16:17]36; GFX90A-NEXT: s_add_u32 s16, s16, foo@gotpcrel32@lo+437; GFX90A-NEXT: s_addc_u32 s17, s17, foo@gotpcrel32@hi+1238; GFX90A-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x039; GFX90A-NEXT: s_waitcnt lgkmcnt(0)40; GFX90A-NEXT: s_swappc_b64 s[30:31], s[16:17]41; GFX90A-NEXT: s_or_saveexec_b64 s[28:29], -142; GFX90A-NEXT: v_accvgpr_read_b32 v39, a3243; GFX90A-NEXT: s_mov_b64 exec, s[28:29]44; GFX90A-NEXT: v_readlane_b32 s20, v39, 045; GFX90A-NEXT: ;;#ASMSTART46; GFX90A-NEXT: ; use s2047; GFX90A-NEXT: ;;#ASMEND48; GFX90A-NEXT: v_readlane_b32 s31, v40, 149; GFX90A-NEXT: v_readlane_b32 s30, v40, 050; GFX90A-NEXT: s_mov_b32 s32, s3351; GFX90A-NEXT: v_readlane_b32 s4, v40, 452; GFX90A-NEXT: v_readlane_b32 s28, v40, 253; GFX90A-NEXT: v_readlane_b32 s29, v40, 354; GFX90A-NEXT: s_xor_saveexec_b64 s[6:7], -155; GFX90A-NEXT: buffer_load_dword v39, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload56; GFX90A-NEXT: s_mov_b64 exec, -157; GFX90A-NEXT: buffer_load_dword a32, off, s[0:3], s33 ; 4-byte Folded Reload58; GFX90A-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload59; GFX90A-NEXT: s_mov_b64 exec, s[6:7]60; GFX90A-NEXT: s_mov_b32 s33, s461; GFX90A-NEXT: s_waitcnt vmcnt(0)62; GFX90A-NEXT: s_setpc_b64 s[30:31]63 %s20 = call i32 asm sideeffect "; def $0","=${s20}"()64 call void @foo()65 call void asm sideeffect "; use $0","${s20}"(i32 %s20)66 ret void67}68 69declare void @foo()70 71attributes #0 = { "amdgpu-num-vgpr"="41" "amdgpu-num-sgpr"="34"}72