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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope --check-prefix=SI %s3; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope --check-prefix=VI %s4; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-TRUE16 %s5; RUN: llc -amdgpu-codegenprepare-widen-constant-loads=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-FAKE16 %s6 7define amdgpu_kernel void @widen_i16_constant_load(ptr addrspace(4) %arg) {8; SI-LABEL: widen_i16_constant_load:9; SI: ; %bb.0:10; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x911; SI-NEXT: s_mov_b32 s3, 0xf00012; SI-NEXT: s_waitcnt lgkmcnt(0)13; SI-NEXT: s_load_dword s2, s[0:1], 0x014; SI-NEXT: s_mov_b64 s[0:1], 015; SI-NEXT: s_waitcnt lgkmcnt(0)16; SI-NEXT: s_addk_i32 s2, 0x3e717; SI-NEXT: s_or_b32 s4, s2, 418; SI-NEXT: s_mov_b32 s2, -119; SI-NEXT: v_mov_b32_e32 v0, s420; SI-NEXT: buffer_store_short v0, off, s[0:3], 021; SI-NEXT: s_endpgm22;23; VI-LABEL: widen_i16_constant_load:24; VI: ; %bb.0:25; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2426; VI-NEXT: v_mov_b32_e32 v0, 027; VI-NEXT: v_mov_b32_e32 v1, 028; VI-NEXT: s_waitcnt lgkmcnt(0)29; VI-NEXT: s_load_dword s0, s[0:1], 0x030; VI-NEXT: s_waitcnt lgkmcnt(0)31; VI-NEXT: s_addk_i32 s0, 0x3e732; VI-NEXT: s_or_b32 s0, s0, 433; VI-NEXT: v_mov_b32_e32 v2, s034; VI-NEXT: flat_store_short v[0:1], v235; VI-NEXT: s_endpgm36;37; GFX11-LABEL: widen_i16_constant_load:38; GFX11: ; %bb.0:39; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x2440; GFX11-NEXT: v_mov_b32_e32 v0, 041; GFX11-NEXT: s_waitcnt lgkmcnt(0)42; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x043; GFX11-NEXT: s_waitcnt lgkmcnt(0)44; GFX11-NEXT: s_addk_i32 s0, 0x3e745; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)46; GFX11-NEXT: s_or_b32 s0, s0, 447; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s048; GFX11-NEXT: global_store_b16 v[0:1], v2, off49; GFX11-NEXT: s_endpgm50 %load = load i16, ptr addrspace(4) %arg, align 451 %add = add i16 %load, 99952 %or = or i16 %add, 453 store i16 %or, ptr addrspace(1) null54 ret void55}56 57define amdgpu_kernel void @widen_i16_constant_load_zext_i32(ptr addrspace(4) %arg) {58; SI-LABEL: widen_i16_constant_load_zext_i32:59; SI: ; %bb.0:60; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x961; SI-NEXT: s_mov_b32 s3, 0xf00062; SI-NEXT: s_waitcnt lgkmcnt(0)63; SI-NEXT: s_load_dword s2, s[0:1], 0x064; SI-NEXT: s_mov_b64 s[0:1], 065; SI-NEXT: s_waitcnt lgkmcnt(0)66; SI-NEXT: s_and_b32 s2, s2, 0xffff67; SI-NEXT: s_addk_i32 s2, 0x3e768; SI-NEXT: s_or_b32 s4, s2, 469; SI-NEXT: s_mov_b32 s2, -170; SI-NEXT: v_mov_b32_e32 v0, s471; SI-NEXT: buffer_store_dword v0, off, s[0:3], 072; SI-NEXT: s_endpgm73;74; VI-LABEL: widen_i16_constant_load_zext_i32:75; VI: ; %bb.0:76; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2477; VI-NEXT: v_mov_b32_e32 v0, 078; VI-NEXT: v_mov_b32_e32 v1, 079; VI-NEXT: s_waitcnt lgkmcnt(0)80; VI-NEXT: s_load_dword s0, s[0:1], 0x081; VI-NEXT: s_waitcnt lgkmcnt(0)82; VI-NEXT: s_and_b32 s0, s0, 0xffff83; VI-NEXT: s_addk_i32 s0, 0x3e784; VI-NEXT: s_or_b32 s0, s0, 485; VI-NEXT: v_mov_b32_e32 v2, s086; VI-NEXT: flat_store_dword v[0:1], v287; VI-NEXT: s_endpgm88;89; GFX11-LABEL: widen_i16_constant_load_zext_i32:90; GFX11: ; %bb.0:91; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x2492; GFX11-NEXT: v_mov_b32_e32 v0, 093; GFX11-NEXT: s_waitcnt lgkmcnt(0)94; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x095; GFX11-NEXT: s_waitcnt lgkmcnt(0)96; GFX11-NEXT: s_and_b32 s0, s0, 0xffff97; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)98; GFX11-NEXT: s_addk_i32 s0, 0x3e799; GFX11-NEXT: s_or_b32 s0, s0, 4100; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)101; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0102; GFX11-NEXT: global_store_b32 v[0:1], v2, off103; GFX11-NEXT: s_endpgm104 %load = load i16, ptr addrspace(4) %arg, align 4105 %ext = zext i16 %load to i32106 %add = add i32 %ext, 999107 %or = or i32 %add, 4108 store i32 %or, ptr addrspace(1) null109 ret void110}111 112define amdgpu_kernel void @widen_i16_constant_load_sext_i32(ptr addrspace(4) %arg) {113; SI-LABEL: widen_i16_constant_load_sext_i32:114; SI: ; %bb.0:115; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9116; SI-NEXT: s_mov_b32 s3, 0xf000117; SI-NEXT: s_waitcnt lgkmcnt(0)118; SI-NEXT: s_load_dword s2, s[0:1], 0x0119; SI-NEXT: s_mov_b64 s[0:1], 0120; SI-NEXT: s_waitcnt lgkmcnt(0)121; SI-NEXT: s_sext_i32_i16 s2, s2122; SI-NEXT: s_addk_i32 s2, 0x3e7123; SI-NEXT: s_or_b32 s4, s2, 4124; SI-NEXT: s_mov_b32 s2, -1125; SI-NEXT: v_mov_b32_e32 v0, s4126; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0127; SI-NEXT: s_endpgm128;129; VI-LABEL: widen_i16_constant_load_sext_i32:130; VI: ; %bb.0:131; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24132; VI-NEXT: v_mov_b32_e32 v0, 0133; VI-NEXT: v_mov_b32_e32 v1, 0134; VI-NEXT: s_waitcnt lgkmcnt(0)135; VI-NEXT: s_load_dword s0, s[0:1], 0x0136; VI-NEXT: s_waitcnt lgkmcnt(0)137; VI-NEXT: s_sext_i32_i16 s0, s0138; VI-NEXT: s_addk_i32 s0, 0x3e7139; VI-NEXT: s_or_b32 s0, s0, 4140; VI-NEXT: v_mov_b32_e32 v2, s0141; VI-NEXT: flat_store_dword v[0:1], v2142; VI-NEXT: s_endpgm143;144; GFX11-LABEL: widen_i16_constant_load_sext_i32:145; GFX11: ; %bb.0:146; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24147; GFX11-NEXT: v_mov_b32_e32 v0, 0148; GFX11-NEXT: s_waitcnt lgkmcnt(0)149; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0150; GFX11-NEXT: s_waitcnt lgkmcnt(0)151; GFX11-NEXT: s_sext_i32_i16 s0, s0152; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)153; GFX11-NEXT: s_addk_i32 s0, 0x3e7154; GFX11-NEXT: s_or_b32 s0, s0, 4155; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)156; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0157; GFX11-NEXT: global_store_b32 v[0:1], v2, off158; GFX11-NEXT: s_endpgm159 %load = load i16, ptr addrspace(4) %arg, align 4160 %ext = sext i16 %load to i32161 %add = add i32 %ext, 999162 %or = or i32 %add, 4163 store i32 %or, ptr addrspace(1) null164 ret void165}166 167define amdgpu_kernel void @widen_i17_constant_load(ptr addrspace(4) %arg) {168; SI-LABEL: widen_i17_constant_load:169; SI: ; %bb.0:170; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9171; SI-NEXT: s_mov_b32 s3, 0xf000172; SI-NEXT: s_mov_b32 s2, -1173; SI-NEXT: s_waitcnt lgkmcnt(0)174; SI-NEXT: s_load_dword s4, s[0:1], 0x0175; SI-NEXT: s_mov_b64 s[0:1], 0176; SI-NEXT: s_waitcnt lgkmcnt(0)177; SI-NEXT: s_add_i32 s4, s4, 34178; SI-NEXT: s_or_b32 s4, s4, 4179; SI-NEXT: v_mov_b32_e32 v0, s4180; SI-NEXT: s_bfe_u32 s4, s4, 0x10010181; SI-NEXT: buffer_store_short v0, off, s[0:3], 0182; SI-NEXT: s_mov_b64 s[0:1], 2183; SI-NEXT: s_waitcnt expcnt(0)184; SI-NEXT: v_mov_b32_e32 v0, s4185; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0186; SI-NEXT: s_endpgm187;188; VI-LABEL: widen_i17_constant_load:189; VI: ; %bb.0:190; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24191; VI-NEXT: v_mov_b32_e32 v0, 0192; VI-NEXT: v_mov_b32_e32 v1, 0193; VI-NEXT: v_mov_b32_e32 v2, 2194; VI-NEXT: v_mov_b32_e32 v3, 0195; VI-NEXT: s_waitcnt lgkmcnt(0)196; VI-NEXT: s_load_dword s0, s[0:1], 0x0197; VI-NEXT: s_waitcnt lgkmcnt(0)198; VI-NEXT: s_add_i32 s0, s0, 34199; VI-NEXT: s_or_b32 s0, s0, 4200; VI-NEXT: v_mov_b32_e32 v4, s0201; VI-NEXT: s_bfe_u32 s0, s0, 0x10010202; VI-NEXT: flat_store_short v[0:1], v4203; VI-NEXT: v_mov_b32_e32 v0, s0204; VI-NEXT: flat_store_byte v[2:3], v0205; VI-NEXT: s_endpgm206;207; GFX11-LABEL: widen_i17_constant_load:208; GFX11: ; %bb.0:209; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24210; GFX11-NEXT: v_mov_b32_e32 v0, 0211; GFX11-NEXT: s_waitcnt lgkmcnt(0)212; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0213; GFX11-NEXT: s_waitcnt lgkmcnt(0)214; GFX11-NEXT: s_add_i32 s0, s0, 34215; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)216; GFX11-NEXT: s_or_b32 s0, s0, 4217; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, s0218; GFX11-NEXT: s_and_b32 s0, s0, 0x1ffff219; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)220; GFX11-NEXT: v_dual_mov_b32 v2, 2 :: v_dual_mov_b32 v5, s0221; GFX11-NEXT: v_mov_b32_e32 v3, 0222; GFX11-NEXT: s_clause 0x1223; GFX11-NEXT: global_store_b16 v[0:1], v4, off224; GFX11-NEXT: global_store_d16_hi_b8 v[2:3], v5, off225; GFX11-NEXT: s_endpgm226 %load = load i17, ptr addrspace(4) %arg, align 4227 %add = add i17 %load, 34228 %or = or i17 %add, 4229 store i17 %or, ptr addrspace(1) null230 ret void231}232 233define amdgpu_kernel void @widen_f16_constant_load(ptr addrspace(4) %arg) {234; SI-LABEL: widen_f16_constant_load:235; SI: ; %bb.0:236; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9237; SI-NEXT: s_mov_b32 s3, 0xf000238; SI-NEXT: s_mov_b32 s2, -1239; SI-NEXT: s_waitcnt lgkmcnt(0)240; SI-NEXT: s_load_dword s0, s[0:1], 0x0241; SI-NEXT: s_waitcnt lgkmcnt(0)242; SI-NEXT: v_cvt_f32_f16_e32 v0, s0243; SI-NEXT: s_mov_b64 s[0:1], 0244; SI-NEXT: v_add_f32_e32 v0, 4.0, v0245; SI-NEXT: v_cvt_f16_f32_e32 v0, v0246; SI-NEXT: buffer_store_short v0, off, s[0:3], 0247; SI-NEXT: s_endpgm248;249; VI-LABEL: widen_f16_constant_load:250; VI: ; %bb.0:251; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24252; VI-NEXT: v_mov_b32_e32 v0, 0253; VI-NEXT: v_mov_b32_e32 v1, 0254; VI-NEXT: s_waitcnt lgkmcnt(0)255; VI-NEXT: s_load_dword s0, s[0:1], 0x0256; VI-NEXT: s_waitcnt lgkmcnt(0)257; VI-NEXT: v_add_f16_e64 v2, s0, 4.0258; VI-NEXT: flat_store_short v[0:1], v2259; VI-NEXT: s_endpgm260;261; GFX11-TRUE16-LABEL: widen_f16_constant_load:262; GFX11-TRUE16: ; %bb.0:263; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24264; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0265; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0266; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)267; GFX11-TRUE16-NEXT: s_load_b32 s0, s[0:1], 0x0268; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)269; GFX11-TRUE16-NEXT: v_add_f16_e64 v0.l, s0, 4.0270; GFX11-TRUE16-NEXT: global_store_b16 v[1:2], v0, off271; GFX11-TRUE16-NEXT: s_endpgm272;273; GFX11-FAKE16-LABEL: widen_f16_constant_load:274; GFX11-FAKE16: ; %bb.0:275; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24276; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0277; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0278; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)279; GFX11-FAKE16-NEXT: s_load_b32 s0, s[0:1], 0x0280; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)281; GFX11-FAKE16-NEXT: v_add_f16_e64 v2, s0, 4.0282; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v2, off283; GFX11-FAKE16-NEXT: s_endpgm284 %load = load half, ptr addrspace(4) %arg, align 4285 %add = fadd half %load, 4.0286 store half %add, ptr addrspace(1) null287 ret void288}289 290; FIXME: valu usage on VI291define amdgpu_kernel void @widen_v2i8_constant_load(ptr addrspace(4) %arg) {292; SI-LABEL: widen_v2i8_constant_load:293; SI: ; %bb.0:294; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9295; SI-NEXT: s_mov_b32 s3, 0xf000296; SI-NEXT: s_waitcnt lgkmcnt(0)297; SI-NEXT: s_load_dword s2, s[0:1], 0x0298; SI-NEXT: s_mov_b64 s[0:1], 0299; SI-NEXT: s_waitcnt lgkmcnt(0)300; SI-NEXT: s_and_b32 s4, s2, 0xff00301; SI-NEXT: s_add_i32 s2, s2, 12302; SI-NEXT: s_or_b32 s2, s2, 4303; SI-NEXT: s_and_b32 s2, s2, 0xff304; SI-NEXT: s_or_b32 s2, s4, s2305; SI-NEXT: s_addk_i32 s2, 0x2c00306; SI-NEXT: s_or_b32 s4, s2, 0x300307; SI-NEXT: s_mov_b32 s2, -1308; SI-NEXT: v_mov_b32_e32 v0, s4309; SI-NEXT: buffer_store_short v0, off, s[0:3], 0310; SI-NEXT: s_endpgm311;312; VI-LABEL: widen_v2i8_constant_load:313; VI: ; %bb.0:314; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24315; VI-NEXT: v_mov_b32_e32 v0, 0316; VI-NEXT: v_mov_b32_e32 v1, 0317; VI-NEXT: s_waitcnt lgkmcnt(0)318; VI-NEXT: s_load_dword s0, s[0:1], 0x0319; VI-NEXT: s_waitcnt lgkmcnt(0)320; VI-NEXT: s_and_b32 s1, s0, 0xff00321; VI-NEXT: s_add_i32 s0, s0, 12322; VI-NEXT: s_or_b32 s0, s0, 4323; VI-NEXT: s_and_b32 s0, s0, 0xff324; VI-NEXT: s_or_b32 s0, s1, s0325; VI-NEXT: s_addk_i32 s0, 0x2c00326; VI-NEXT: s_or_b32 s0, s0, 0x300327; VI-NEXT: v_mov_b32_e32 v2, s0328; VI-NEXT: flat_store_short v[0:1], v2329; VI-NEXT: s_endpgm330;331; GFX11-LABEL: widen_v2i8_constant_load:332; GFX11: ; %bb.0:333; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24334; GFX11-NEXT: v_mov_b32_e32 v0, 0335; GFX11-NEXT: s_waitcnt lgkmcnt(0)336; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0337; GFX11-NEXT: s_waitcnt lgkmcnt(0)338; GFX11-NEXT: s_add_i32 s1, s0, 12339; GFX11-NEXT: s_and_b32 s0, s0, 0xff00340; GFX11-NEXT: s_or_b32 s1, s1, 4341; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)342; GFX11-NEXT: s_and_b32 s1, s1, 0xff343; GFX11-NEXT: s_or_b32 s0, s0, s1344; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)345; GFX11-NEXT: s_addk_i32 s0, 0x2c00346; GFX11-NEXT: s_or_b32 s0, s0, 0x300347; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)348; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0349; GFX11-NEXT: global_store_b16 v[0:1], v2, off350; GFX11-NEXT: s_endpgm351 %load = load <2 x i8>, ptr addrspace(4) %arg, align 4352 %add = add <2 x i8> %load, <i8 12, i8 44>353 %or = or <2 x i8> %add, <i8 4, i8 3>354 store <2 x i8> %or, ptr addrspace(1) null355 ret void356}357 358define amdgpu_kernel void @no_widen_i16_constant_divergent_load(ptr addrspace(4) %arg) {359; SI-LABEL: no_widen_i16_constant_divergent_load:360; SI: ; %bb.0:361; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9362; SI-NEXT: s_mov_b32 s2, 0363; SI-NEXT: s_mov_b32 s3, 0xf000364; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0365; SI-NEXT: v_mov_b32_e32 v1, 0366; SI-NEXT: s_waitcnt lgkmcnt(0)367; SI-NEXT: buffer_load_ushort v0, v[0:1], s[0:3], 0 addr64368; SI-NEXT: s_mov_b64 s[0:1], 0369; SI-NEXT: s_mov_b32 s2, -1370; SI-NEXT: s_waitcnt vmcnt(0)371; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3e7, v0372; SI-NEXT: v_or_b32_e32 v0, 4, v0373; SI-NEXT: buffer_store_short v0, off, s[0:3], 0374; SI-NEXT: s_endpgm375;376; VI-LABEL: no_widen_i16_constant_divergent_load:377; VI: ; %bb.0:378; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24379; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v0380; VI-NEXT: s_waitcnt lgkmcnt(0)381; VI-NEXT: v_mov_b32_e32 v1, s1382; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0383; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc384; VI-NEXT: flat_load_ushort v0, v[0:1]385; VI-NEXT: s_waitcnt vmcnt(0)386; VI-NEXT: v_add_u16_e32 v2, 0x3e7, v0387; VI-NEXT: v_mov_b32_e32 v0, 0388; VI-NEXT: v_mov_b32_e32 v1, 0389; VI-NEXT: v_or_b32_e32 v2, 4, v2390; VI-NEXT: flat_store_short v[0:1], v2391; VI-NEXT: s_endpgm392;393; GFX11-TRUE16-LABEL: no_widen_i16_constant_divergent_load:394; GFX11-TRUE16: ; %bb.0:395; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24396; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0397; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0398; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)399; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 1, v0400; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)401; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1]402; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)403; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x3e7, v0.l404; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, 4405; GFX11-TRUE16-NEXT: global_store_b16 v[1:2], v0, off406; GFX11-TRUE16-NEXT: s_endpgm407;408; GFX11-FAKE16-LABEL: no_widen_i16_constant_divergent_load:409; GFX11-FAKE16: ; %bb.0:410; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24411; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0412; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)413; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 1, v0414; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)415; GFX11-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1]416; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)417; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x3e7, v0418; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0419; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0420; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)421; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 4, v2422; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v2, off423; GFX11-FAKE16-NEXT: s_endpgm424 %tid = call i32 @llvm.amdgcn.workitem.id.x()425 %tid.ext = zext i32 %tid to i64426 %gep.arg = getelementptr inbounds i16, ptr addrspace(4) %arg, i64 %tid.ext427 %load = load i16, ptr addrspace(4) %gep.arg, align 4428 %add = add i16 %load, 999429 %or = or i16 %add, 4430 store i16 %or, ptr addrspace(1) null431 ret void432}433 434define amdgpu_kernel void @widen_i1_constant_load(ptr addrspace(4) %arg) {435; SI-LABEL: widen_i1_constant_load:436; SI: ; %bb.0:437; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9438; SI-NEXT: s_mov_b32 s3, 0xf000439; SI-NEXT: s_waitcnt lgkmcnt(0)440; SI-NEXT: s_load_dword s2, s[0:1], 0x0441; SI-NEXT: s_mov_b64 s[0:1], 0442; SI-NEXT: s_waitcnt lgkmcnt(0)443; SI-NEXT: s_and_b32 s4, s2, 1444; SI-NEXT: s_mov_b32 s2, -1445; SI-NEXT: v_mov_b32_e32 v0, s4446; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0447; SI-NEXT: s_endpgm448;449; VI-LABEL: widen_i1_constant_load:450; VI: ; %bb.0:451; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24452; VI-NEXT: v_mov_b32_e32 v0, 0453; VI-NEXT: v_mov_b32_e32 v1, 0454; VI-NEXT: s_waitcnt lgkmcnt(0)455; VI-NEXT: s_load_dword s0, s[0:1], 0x0456; VI-NEXT: s_waitcnt lgkmcnt(0)457; VI-NEXT: s_and_b32 s0, s0, 1458; VI-NEXT: v_mov_b32_e32 v2, s0459; VI-NEXT: flat_store_byte v[0:1], v2460; VI-NEXT: s_endpgm461;462; GFX11-LABEL: widen_i1_constant_load:463; GFX11: ; %bb.0:464; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24465; GFX11-NEXT: v_mov_b32_e32 v0, 0466; GFX11-NEXT: s_waitcnt lgkmcnt(0)467; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0468; GFX11-NEXT: s_waitcnt lgkmcnt(0)469; GFX11-NEXT: s_and_b32 s0, s0, 1470; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)471; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0472; GFX11-NEXT: global_store_b8 v[0:1], v2, off473; GFX11-NEXT: s_endpgm474 %load = load i1, ptr addrspace(4) %arg, align 4475 %and = and i1 %load, true476 store i1 %and, ptr addrspace(1) null477 ret void478}479 480define amdgpu_kernel void @widen_i16_zextload_i64_constant_load(ptr addrspace(4) %arg) {481; SI-LABEL: widen_i16_zextload_i64_constant_load:482; SI: ; %bb.0:483; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9484; SI-NEXT: s_mov_b32 s3, 0xf000485; SI-NEXT: s_waitcnt lgkmcnt(0)486; SI-NEXT: s_load_dword s2, s[0:1], 0x0487; SI-NEXT: s_mov_b64 s[0:1], 0488; SI-NEXT: s_waitcnt lgkmcnt(0)489; SI-NEXT: s_and_b32 s2, s2, 0xffff490; SI-NEXT: s_addk_i32 s2, 0x3e7491; SI-NEXT: s_or_b32 s4, s2, 4492; SI-NEXT: s_mov_b32 s2, -1493; SI-NEXT: v_mov_b32_e32 v0, s4494; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0495; SI-NEXT: s_endpgm496;497; VI-LABEL: widen_i16_zextload_i64_constant_load:498; VI: ; %bb.0:499; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24500; VI-NEXT: v_mov_b32_e32 v0, 0501; VI-NEXT: v_mov_b32_e32 v1, 0502; VI-NEXT: s_waitcnt lgkmcnt(0)503; VI-NEXT: s_load_dword s0, s[0:1], 0x0504; VI-NEXT: s_waitcnt lgkmcnt(0)505; VI-NEXT: s_and_b32 s0, s0, 0xffff506; VI-NEXT: s_addk_i32 s0, 0x3e7507; VI-NEXT: s_or_b32 s0, s0, 4508; VI-NEXT: v_mov_b32_e32 v2, s0509; VI-NEXT: flat_store_dword v[0:1], v2510; VI-NEXT: s_endpgm511;512; GFX11-LABEL: widen_i16_zextload_i64_constant_load:513; GFX11: ; %bb.0:514; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24515; GFX11-NEXT: v_mov_b32_e32 v0, 0516; GFX11-NEXT: s_waitcnt lgkmcnt(0)517; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0518; GFX11-NEXT: s_waitcnt lgkmcnt(0)519; GFX11-NEXT: s_and_b32 s0, s0, 0xffff520; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)521; GFX11-NEXT: s_addk_i32 s0, 0x3e7522; GFX11-NEXT: s_or_b32 s0, s0, 4523; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)524; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0525; GFX11-NEXT: global_store_b32 v[0:1], v2, off526; GFX11-NEXT: s_endpgm527 %load = load i16, ptr addrspace(4) %arg, align 4528 %zext = zext i16 %load to i32529 %add = add i32 %zext, 999530 %or = or i32 %add, 4531 store i32 %or, ptr addrspace(1) null532 ret void533}534 535define amdgpu_kernel void @widen_i1_zext_to_i64_constant_load(ptr addrspace(4) %arg) {536; SI-LABEL: widen_i1_zext_to_i64_constant_load:537; SI: ; %bb.0:538; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9539; SI-NEXT: v_mov_b32_e32 v1, 0540; SI-NEXT: s_mov_b32 s3, 0xf000541; SI-NEXT: s_waitcnt lgkmcnt(0)542; SI-NEXT: s_load_dword s2, s[0:1], 0x0543; SI-NEXT: s_mov_b64 s[0:1], 0544; SI-NEXT: s_waitcnt lgkmcnt(0)545; SI-NEXT: s_and_b32 s2, s2, 0xff546; SI-NEXT: s_addk_i32 s2, 0x3e7547; SI-NEXT: v_mov_b32_e32 v0, s2548; SI-NEXT: s_mov_b32 s2, -1549; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0550; SI-NEXT: s_endpgm551;552; VI-LABEL: widen_i1_zext_to_i64_constant_load:553; VI: ; %bb.0:554; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24555; VI-NEXT: v_mov_b32_e32 v0, 0556; VI-NEXT: v_mov_b32_e32 v1, 0557; VI-NEXT: v_mov_b32_e32 v3, 0558; VI-NEXT: s_waitcnt lgkmcnt(0)559; VI-NEXT: s_load_dword s0, s[0:1], 0x0560; VI-NEXT: s_waitcnt lgkmcnt(0)561; VI-NEXT: s_and_b32 s0, s0, 0xff562; VI-NEXT: s_addk_i32 s0, 0x3e7563; VI-NEXT: v_mov_b32_e32 v2, s0564; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]565; VI-NEXT: s_endpgm566;567; GFX11-LABEL: widen_i1_zext_to_i64_constant_load:568; GFX11: ; %bb.0:569; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24570; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, 0571; GFX11-NEXT: s_waitcnt lgkmcnt(0)572; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0573; GFX11-NEXT: s_waitcnt lgkmcnt(0)574; GFX11-NEXT: s_and_b32 s0, s0, 0xff575; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)576; GFX11-NEXT: s_addk_i32 s0, 0x3e7577; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0578; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off579; GFX11-NEXT: s_endpgm580 %load = load i1, ptr addrspace(4) %arg, align 4581 %zext = zext i1 %load to i64582 %add = add i64 %zext, 999583 store i64 %add, ptr addrspace(1) null584 ret void585}586 587define amdgpu_kernel void @widen_i16_constant32_load(ptr addrspace(6) %arg) {588; SI-LABEL: widen_i16_constant32_load:589; SI: ; %bb.0:590; SI-NEXT: s_load_dword s0, s[4:5], 0x9591; SI-NEXT: s_mov_b32 s1, 0592; SI-NEXT: s_mov_b32 s3, 0xf000593; SI-NEXT: s_waitcnt lgkmcnt(0)594; SI-NEXT: s_load_dword s2, s[0:1], 0x0595; SI-NEXT: s_mov_b64 s[0:1], 0596; SI-NEXT: s_waitcnt lgkmcnt(0)597; SI-NEXT: s_addk_i32 s2, 0x3e7598; SI-NEXT: s_or_b32 s4, s2, 4599; SI-NEXT: s_mov_b32 s2, -1600; SI-NEXT: v_mov_b32_e32 v0, s4601; SI-NEXT: buffer_store_short v0, off, s[0:3], 0602; SI-NEXT: s_endpgm603;604; VI-LABEL: widen_i16_constant32_load:605; VI: ; %bb.0:606; VI-NEXT: s_load_dword s0, s[4:5], 0x24607; VI-NEXT: s_mov_b32 s1, 0608; VI-NEXT: v_mov_b32_e32 v0, 0609; VI-NEXT: v_mov_b32_e32 v1, 0610; VI-NEXT: s_waitcnt lgkmcnt(0)611; VI-NEXT: s_load_dword s0, s[0:1], 0x0612; VI-NEXT: s_waitcnt lgkmcnt(0)613; VI-NEXT: s_addk_i32 s0, 0x3e7614; VI-NEXT: s_or_b32 s0, s0, 4615; VI-NEXT: v_mov_b32_e32 v2, s0616; VI-NEXT: flat_store_short v[0:1], v2617; VI-NEXT: s_endpgm618;619; GFX11-LABEL: widen_i16_constant32_load:620; GFX11: ; %bb.0:621; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24622; GFX11-NEXT: s_mov_b32 s1, 0623; GFX11-NEXT: v_mov_b32_e32 v0, 0624; GFX11-NEXT: s_waitcnt lgkmcnt(0)625; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0626; GFX11-NEXT: s_waitcnt lgkmcnt(0)627; GFX11-NEXT: s_addk_i32 s0, 0x3e7628; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)629; GFX11-NEXT: s_or_b32 s0, s0, 4630; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0631; GFX11-NEXT: global_store_b16 v[0:1], v2, off632; GFX11-NEXT: s_endpgm633 %load = load i16, ptr addrspace(6) %arg, align 4634 %add = add i16 %load, 999635 %or = or i16 %add, 4636 store i16 %or, ptr addrspace(1) null637 ret void638}639 640define amdgpu_kernel void @widen_i16_global_invariant_load(ptr addrspace(1) %arg) {641; SI-LABEL: widen_i16_global_invariant_load:642; SI: ; %bb.0:643; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9644; SI-NEXT: s_mov_b32 s3, 0xf000645; SI-NEXT: s_waitcnt lgkmcnt(0)646; SI-NEXT: s_load_dword s2, s[0:1], 0x0647; SI-NEXT: s_mov_b64 s[0:1], 0648; SI-NEXT: s_waitcnt lgkmcnt(0)649; SI-NEXT: s_addk_i32 s2, 0x3e7650; SI-NEXT: s_or_b32 s4, s2, 1651; SI-NEXT: s_mov_b32 s2, -1652; SI-NEXT: v_mov_b32_e32 v0, s4653; SI-NEXT: buffer_store_short v0, off, s[0:3], 0654; SI-NEXT: s_endpgm655;656; VI-LABEL: widen_i16_global_invariant_load:657; VI: ; %bb.0:658; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24659; VI-NEXT: v_mov_b32_e32 v0, 0660; VI-NEXT: v_mov_b32_e32 v1, 0661; VI-NEXT: s_waitcnt lgkmcnt(0)662; VI-NEXT: s_load_dword s0, s[0:1], 0x0663; VI-NEXT: s_waitcnt lgkmcnt(0)664; VI-NEXT: s_addk_i32 s0, 0x3e7665; VI-NEXT: s_or_b32 s0, s0, 1666; VI-NEXT: v_mov_b32_e32 v2, s0667; VI-NEXT: flat_store_short v[0:1], v2668; VI-NEXT: s_endpgm669;670; GFX11-LABEL: widen_i16_global_invariant_load:671; GFX11: ; %bb.0:672; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24673; GFX11-NEXT: v_mov_b32_e32 v0, 0674; GFX11-NEXT: s_waitcnt lgkmcnt(0)675; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0676; GFX11-NEXT: s_waitcnt lgkmcnt(0)677; GFX11-NEXT: s_addk_i32 s0, 0x3e7678; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)679; GFX11-NEXT: s_or_b32 s0, s0, 1680; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s0681; GFX11-NEXT: global_store_b16 v[0:1], v2, off682; GFX11-NEXT: s_endpgm683 %load = load i16, ptr addrspace(1) %arg, align 4, !invariant.load !0684 %add = add i16 %load, 999685 %or = or i16 %add, 1686 store i16 %or, ptr addrspace(1) null687 ret void688}689 690declare i32 @llvm.amdgcn.workitem.id.x()691 692!0 = !{}693