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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCN %s3 4; Check that DAGTypeLegalizer::WidenVSELECTAndMask doesn't try to5; create vselects with i64 condition masks.6 7; FIXME: Should be able to avoid intermediate vselect8define amdgpu_kernel void @widen_vselect_and_mask_v4f64(<4 x double> %arg) #0 {9; GCN-LABEL: widen_vselect_and_mask_v4f64:10; GCN: ; %bb.0: ; %bb11; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x912; GCN-NEXT: v_mov_b32_e32 v0, 013; GCN-NEXT: s_waitcnt lgkmcnt(0)14; GCN-NEXT: s_mov_b64 s[4:5], 1615; GCN-NEXT: s_mov_b32 s7, 0xf00016; GCN-NEXT: s_mov_b32 s6, -117; GCN-NEXT: v_mov_b32_e32 v1, v018; GCN-NEXT: v_mov_b32_e32 v2, v019; GCN-NEXT: v_mov_b32_e32 v3, v020; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 021; GCN-NEXT: v_cmp_u_f64_e64 s[2:3], s[0:1], s[0:1]22; GCN-NEXT: s_waitcnt expcnt(0)23; GCN-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[2:3]24; GCN-NEXT: v_cmp_neq_f64_e64 s[0:1], s[0:1], 025; GCN-NEXT: v_mov_b32_e32 v2, v126; GCN-NEXT: v_cmp_lt_i64_e32 vcc, -1, v[1:2]27; GCN-NEXT: s_and_b64 s[0:1], vcc, s[0:1]28; GCN-NEXT: s_and_b64 s[0:1], s[0:1], exec29; GCN-NEXT: s_cselect_b32 s0, 0x3ff00000, 030; GCN-NEXT: s_mov_b64 s[4:5], 031; GCN-NEXT: v_mov_b32_e32 v2, v032; GCN-NEXT: v_mov_b32_e32 v1, s033; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 034; GCN-NEXT: s_endpgm35bb:36 %tmp = extractelement <4 x double> %arg, i64 037 %tmp1 = fcmp uno double %tmp, 0.000000e+0038 %tmp2 = sext i1 %tmp1 to i6439 %tmp3 = insertelement <4 x i64> poison, i64 %tmp2, i32 040 %tmp4 = insertelement <4 x i64> %tmp3, i64 poison, i32 141 %tmp5 = insertelement <4 x i64> %tmp4, i64 poison, i32 242 %tmp6 = insertelement <4 x i64> %tmp5, i64 poison, i32 343 %tmp7 = fcmp une <4 x double> %arg, zeroinitializer44 %tmp8 = icmp sgt <4 x i64> %tmp6, <i64 -1, i64 -1, i64 -1, i64 -1>45 %tmp9 = and <4 x i1> %tmp8, %tmp746 %tmp10 = select <4 x i1> %tmp9, <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>, <4 x double> zeroinitializer47 store <4 x double> %tmp10, ptr addrspace(1) null, align 3248 ret void49}50 51define amdgpu_kernel void @widen_vselect_and_mask_v4i64(<4 x i64> %arg) #0 {52; GCN-LABEL: widen_vselect_and_mask_v4i64:53; GCN: ; %bb.0: ; %bb54; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x955; GCN-NEXT: s_waitcnt lgkmcnt(0)56; GCN-NEXT: s_mov_b64 s[4:5], 057; GCN-NEXT: v_mov_b32_e32 v1, 058; GCN-NEXT: s_mov_b64 s[8:9], 1659; GCN-NEXT: s_mov_b32 s11, 0xf00060; GCN-NEXT: s_mov_b32 s10, -161; GCN-NEXT: v_mov_b32_e32 v2, v162; GCN-NEXT: v_mov_b32_e32 v3, v163; GCN-NEXT: v_mov_b32_e32 v4, v164; GCN-NEXT: v_cmp_eq_u64_e64 s[2:3], s[0:1], 065; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[2:3]66; GCN-NEXT: v_cmp_ne_u64_e64 s[0:1], s[0:1], 067; GCN-NEXT: v_mov_b32_e32 v6, v568; GCN-NEXT: v_cmp_lt_i64_e32 vcc, -1, v[5:6]69; GCN-NEXT: s_and_b64 s[0:1], vcc, s[0:1]70; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]71; GCN-NEXT: buffer_store_dwordx4 v[1:4], off, s[8:11], 072; GCN-NEXT: s_mov_b32 s6, s1073; GCN-NEXT: s_mov_b32 s7, s1174; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 075; GCN-NEXT: s_endpgm76bb:77 %tmp = extractelement <4 x i64> %arg, i64 078 %tmp1 = icmp eq i64 %tmp, 079 %tmp2 = sext i1 %tmp1 to i6480 %tmp3 = insertelement <4 x i64> poison, i64 %tmp2, i32 081 %tmp4 = insertelement <4 x i64> %tmp3, i64 poison, i32 182 %tmp5 = insertelement <4 x i64> %tmp4, i64 poison, i32 283 %tmp6 = insertelement <4 x i64> %tmp5, i64 poison, i32 384 %tmp7 = icmp ne <4 x i64> %arg, zeroinitializer85 %tmp8 = icmp sgt <4 x i64> %tmp6, <i64 -1, i64 -1, i64 -1, i64 -1>86 %tmp9 = and <4 x i1> %tmp8, %tmp787 %tmp10 = select <4 x i1> %tmp9, <4 x i64> <i64 1, i64 1, i64 1, i64 1>, <4 x i64> zeroinitializer88 store <4 x i64> %tmp10, ptr addrspace(1) null, align 3289 ret void90}91 92attributes #0 = { nounwind }93attributes #1 = { nounwind readnone speculatable }94