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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -mtriple=amdgcn-- -amdgpu-codegenprepare -amdgpu-codegenprepare-widen-constant-loads < %s | FileCheck -check-prefix=OPT %s3 4declare ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #05 6define amdgpu_kernel void @constant_load_i1(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {7; OPT-LABEL: @constant_load_i1(8; OPT-NEXT: [[VAL:%.*]] = load i1, ptr addrspace(4) [[IN:%.*]], align 19; OPT-NEXT: store i1 [[VAL]], ptr addrspace(1) [[OUT:%.*]], align 110; OPT-NEXT: ret void11;12 %val = load i1, ptr addrspace(4) %in13 store i1 %val, ptr addrspace(1) %out14 ret void15}16 17define amdgpu_kernel void @constant_load_i1_align2(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {18; OPT-LABEL: @constant_load_i1_align2(19; OPT-NEXT: [[VAL:%.*]] = load i1, ptr addrspace(4) [[IN:%.*]], align 220; OPT-NEXT: store i1 [[VAL]], ptr addrspace(1) [[OUT:%.*]], align 221; OPT-NEXT: ret void22;23 %val = load i1, ptr addrspace(4) %in, align 224 store i1 %val, ptr addrspace(1) %out, align 225 ret void26}27 28define amdgpu_kernel void @constant_load_i1_align4(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {29; OPT-LABEL: @constant_load_i1_align4(30; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[IN:%.*]], align 431; OPT-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i132; OPT-NEXT: store i1 [[TMP3]], ptr addrspace(1) [[OUT:%.*]], align 433; OPT-NEXT: ret void34;35 %val = load i1, ptr addrspace(4) %in, align 436 store i1 %val, ptr addrspace(1) %out, align 437 ret void38}39 40define amdgpu_kernel void @constant_load_i8(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {41; OPT-LABEL: @constant_load_i8(42; OPT-NEXT: [[VAL:%.*]] = load i8, ptr addrspace(4) [[IN:%.*]], align 143; OPT-NEXT: store i8 [[VAL]], ptr addrspace(1) [[OUT:%.*]], align 144; OPT-NEXT: ret void45;46 %val = load i8, ptr addrspace(4) %in47 store i8 %val, ptr addrspace(1) %out48 ret void49}50 51define amdgpu_kernel void @constant_load_i8_align2(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {52; OPT-LABEL: @constant_load_i8_align2(53; OPT-NEXT: [[VAL:%.*]] = load i8, ptr addrspace(4) [[IN:%.*]], align 254; OPT-NEXT: store i8 [[VAL]], ptr addrspace(1) [[OUT:%.*]], align 255; OPT-NEXT: ret void56;57 %val = load i8, ptr addrspace(4) %in, align 258 store i8 %val, ptr addrspace(1) %out, align 259 ret void60}61 62define amdgpu_kernel void @constant_load_i8align4(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {63; OPT-LABEL: @constant_load_i8align4(64; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[IN:%.*]], align 465; OPT-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i866; OPT-NEXT: store i8 [[TMP3]], ptr addrspace(1) [[OUT:%.*]], align 467; OPT-NEXT: ret void68;69 %val = load i8, ptr addrspace(4) %in, align 470 store i8 %val, ptr addrspace(1) %out, align 471 ret void72}73 74define amdgpu_kernel void @constant_load_v2i8(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {75; OPT-LABEL: @constant_load_v2i8(76; OPT-NEXT: [[LD:%.*]] = load <2 x i8>, ptr addrspace(4) [[IN:%.*]], align 277; OPT-NEXT: store <2 x i8> [[LD]], ptr addrspace(1) [[OUT:%.*]], align 278; OPT-NEXT: ret void79;80 %ld = load <2 x i8>, ptr addrspace(4) %in81 store <2 x i8> %ld, ptr addrspace(1) %out82 ret void83}84 85define amdgpu_kernel void @constant_load_v2i8_align4(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {86; OPT-LABEL: @constant_load_v2i8_align4(87; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[IN:%.*]], align 488; OPT-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i1689; OPT-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP3]] to <2 x i8>90; OPT-NEXT: store <2 x i8> [[TMP4]], ptr addrspace(1) [[OUT:%.*]], align 491; OPT-NEXT: ret void92;93 %ld = load <2 x i8>, ptr addrspace(4) %in, align 494 store <2 x i8> %ld, ptr addrspace(1) %out, align 495 ret void96}97 98define amdgpu_kernel void @constant_load_v3i8(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {99; OPT-LABEL: @constant_load_v3i8(100; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[IN:%.*]], align 4101; OPT-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i24102; OPT-NEXT: [[TMP4:%.*]] = bitcast i24 [[TMP3]] to <3 x i8>103; OPT-NEXT: store <3 x i8> [[TMP4]], ptr addrspace(1) [[OUT:%.*]], align 4104; OPT-NEXT: ret void105;106 %ld = load <3 x i8>, ptr addrspace(4) %in107 store <3 x i8> %ld, ptr addrspace(1) %out108 ret void109}110 111define amdgpu_kernel void @constant_load_v3i8_align4(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {112; OPT-LABEL: @constant_load_v3i8_align4(113; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[IN:%.*]], align 4114; OPT-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i24115; OPT-NEXT: [[TMP4:%.*]] = bitcast i24 [[TMP3]] to <3 x i8>116; OPT-NEXT: store <3 x i8> [[TMP4]], ptr addrspace(1) [[OUT:%.*]], align 4117; OPT-NEXT: ret void118;119 %ld = load <3 x i8>, ptr addrspace(4) %in, align 4120 store <3 x i8> %ld, ptr addrspace(1) %out, align 4121 ret void122}123 124define amdgpu_kernel void @constant_load_i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {125; OPT-LABEL: @constant_load_i16(126; OPT-NEXT: [[LD:%.*]] = load i16, ptr addrspace(4) [[IN:%.*]], align 2127; OPT-NEXT: [[EXT:%.*]] = sext i16 [[LD]] to i32128; OPT-NEXT: store i32 [[EXT]], ptr addrspace(1) [[OUT:%.*]], align 4129; OPT-NEXT: ret void130;131 %ld = load i16, ptr addrspace(4) %in132 %ext = sext i16 %ld to i32133 store i32 %ext, ptr addrspace(1) %out134 ret void135}136 137define amdgpu_kernel void @constant_load_i16_align4(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {138; OPT-LABEL: @constant_load_i16_align4(139; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[IN:%.*]], align 4140; OPT-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16141; OPT-NEXT: [[EXT:%.*]] = sext i16 [[TMP3]] to i32142; OPT-NEXT: store i32 [[EXT]], ptr addrspace(1) [[OUT:%.*]], align 4143; OPT-NEXT: ret void144;145 %ld = load i16, ptr addrspace(4) %in, align 4146 %ext = sext i16 %ld to i32147 store i32 %ext, ptr addrspace(1) %out, align 4148 ret void149}150 151define amdgpu_kernel void @constant_load_f16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {152; OPT-LABEL: @constant_load_f16(153; OPT-NEXT: [[LD:%.*]] = load half, ptr addrspace(4) [[IN:%.*]], align 2154; OPT-NEXT: store half [[LD]], ptr addrspace(1) [[OUT:%.*]], align 2155; OPT-NEXT: ret void156;157 %ld = load half, ptr addrspace(4) %in158 store half %ld, ptr addrspace(1) %out159 ret void160}161 162define amdgpu_kernel void @constant_load_v2f16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {163; OPT-LABEL: @constant_load_v2f16(164; OPT-NEXT: [[LD:%.*]] = load <2 x half>, ptr addrspace(4) [[IN:%.*]], align 4165; OPT-NEXT: store <2 x half> [[LD]], ptr addrspace(1) [[OUT:%.*]], align 4166; OPT-NEXT: ret void167;168 %ld = load <2 x half>, ptr addrspace(4) %in169 store <2 x half> %ld, ptr addrspace(1) %out170 ret void171}172 173define amdgpu_kernel void @load_volatile(ptr addrspace(1) %out, ptr addrspace(4) %in) {174; OPT-LABEL: @load_volatile(175; OPT-NEXT: [[A:%.*]] = load volatile i16, ptr addrspace(4) [[IN:%.*]], align 2176; OPT-NEXT: store i16 [[A]], ptr addrspace(1) [[OUT:%.*]], align 2177; OPT-NEXT: ret void178;179 %a = load volatile i16, ptr addrspace(4) %in180 store i16 %a, ptr addrspace(1) %out181 ret void182}183 184define amdgpu_kernel void @constant_load_v2i8_volatile(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {185; OPT-LABEL: @constant_load_v2i8_volatile(186; OPT-NEXT: [[LD:%.*]] = load volatile <2 x i8>, ptr addrspace(4) [[IN:%.*]], align 2187; OPT-NEXT: store <2 x i8> [[LD]], ptr addrspace(1) [[OUT:%.*]], align 2188; OPT-NEXT: ret void189;190 %ld = load volatile <2 x i8>, ptr addrspace(4) %in191 store <2 x i8> %ld, ptr addrspace(1) %out192 ret void193}194 195define amdgpu_kernel void @constant_load_v2i8_addrspace1(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {196; OPT-LABEL: @constant_load_v2i8_addrspace1(197; OPT-NEXT: [[LD:%.*]] = load <2 x i8>, ptr addrspace(1) [[IN:%.*]], align 2198; OPT-NEXT: store <2 x i8> [[LD]], ptr addrspace(1) [[OUT:%.*]], align 2199; OPT-NEXT: ret void200;201 %ld = load <2 x i8>, ptr addrspace(1) %in202 store <2 x i8> %ld, ptr addrspace(1) %out203 ret void204}205 206define amdgpu_kernel void @use_dispatch_ptr(ptr addrspace(1) %ptr) #1 {207; OPT-LABEL: @use_dispatch_ptr(208; OPT-NEXT: [[DISPATCH_PTR:%.*]] = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()209; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[DISPATCH_PTR]], align 4210; OPT-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8211; OPT-NEXT: [[LD:%.*]] = zext i8 [[TMP3]] to i32212; OPT-NEXT: store i32 [[LD]], ptr addrspace(1) [[PTR:%.*]], align 4213; OPT-NEXT: ret void214;215 %dispatch.ptr = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()216 %val = load i8, ptr addrspace(4) %dispatch.ptr, align 4217 %ld = zext i8 %val to i32218 store i32 %ld, ptr addrspace(1) %ptr219 ret void220}221 222define amdgpu_kernel void @constant_load_i16_align4_range(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {223; OPT-LABEL: @constant_load_i16_align4_range(224; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[IN:%.*]], align 4, !range [[RNG0:![0-9]+]]225; OPT-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16226; OPT-NEXT: [[EXT:%.*]] = sext i16 [[TMP3]] to i32227; OPT-NEXT: store i32 [[EXT]], ptr addrspace(1) [[OUT:%.*]], align 4228; OPT-NEXT: ret void229;230 %ld = load i16, ptr addrspace(4) %in, align 4, !range !0231 %ext = sext i16 %ld to i32232 store i32 %ext, ptr addrspace(1) %out233 ret void234}235 236define amdgpu_kernel void @constant_load_i16_align4_range_max(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {237; OPT-LABEL: @constant_load_i16_align4_range_max(238; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[IN:%.*]], align 4, !range [[RNG0]]239; OPT-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16240; OPT-NEXT: [[EXT:%.*]] = sext i16 [[TMP3]] to i32241; OPT-NEXT: store i32 [[EXT]], ptr addrspace(1) [[OUT:%.*]], align 4242; OPT-NEXT: ret void243;244 %ld = load i16, ptr addrspace(4) %in, align 4, !range !1245 %ext = sext i16 %ld to i32246 store i32 %ext, ptr addrspace(1) %out247 ret void248}249 250define amdgpu_kernel void @constant_load_i16_align4_complex_range(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {251; OPT-LABEL: @constant_load_i16_align4_complex_range(252; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[IN:%.*]], align 4, !range [[RNG1:![0-9]+]]253; OPT-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16254; OPT-NEXT: [[EXT:%.*]] = sext i16 [[TMP3]] to i32255; OPT-NEXT: store i32 [[EXT]], ptr addrspace(1) [[OUT:%.*]], align 4256; OPT-NEXT: ret void257;258 %ld = load i16, ptr addrspace(4) %in, align 4, !range !2259 %ext = sext i16 %ld to i32260 store i32 %ext, ptr addrspace(1) %out261 ret void262}263 264define amdgpu_kernel void @constant_load_i16_align4_range_from_0(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {265; OPT-LABEL: @constant_load_i16_align4_range_from_0(266; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[IN:%.*]], align 4267; OPT-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16268; OPT-NEXT: [[EXT:%.*]] = sext i16 [[TMP3]] to i32269; OPT-NEXT: store i32 [[EXT]], ptr addrspace(1) [[OUT:%.*]], align 4270; OPT-NEXT: ret void271;272 %ld = load i16, ptr addrspace(4) %in, align 4, !range !3273 %ext = sext i16 %ld to i32274 store i32 %ext, ptr addrspace(1) %out275 ret void276}277 278define amdgpu_kernel void @constant_load_i16_align4_range_from_neg(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {279; OPT-LABEL: @constant_load_i16_align4_range_from_neg(280; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[IN:%.*]], align 4, !range [[RNG2:![0-9]+]]281; OPT-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16282; OPT-NEXT: [[EXT:%.*]] = sext i16 [[TMP3]] to i32283; OPT-NEXT: store i32 [[EXT]], ptr addrspace(1) [[OUT:%.*]], align 4284; OPT-NEXT: ret void285;286 %ld = load i16, ptr addrspace(4) %in, align 4, !range !4287 %ext = sext i16 %ld to i32288 store i32 %ext, ptr addrspace(1) %out289 ret void290}291 292define amdgpu_kernel void @constant_load_i16_align4_range_from_neg_to_0(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {293; OPT-LABEL: @constant_load_i16_align4_range_from_neg_to_0(294; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[IN:%.*]], align 4, !range [[RNG2]]295; OPT-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16296; OPT-NEXT: [[EXT:%.*]] = sext i16 [[TMP3]] to i32297; OPT-NEXT: store i32 [[EXT]], ptr addrspace(1) [[OUT:%.*]], align 4298; OPT-NEXT: ret void299;300 %ld = load i16, ptr addrspace(4) %in, align 4, !range !5301 %ext = sext i16 %ld to i32302 store i32 %ext, ptr addrspace(1) %out303 ret void304}305 306define amdgpu_kernel void @constant_load_i16_align4_invariant(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {307; OPT-LABEL: @constant_load_i16_align4_invariant(308; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[IN:%.*]], align 4, !invariant.load !3309; OPT-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16310; OPT-NEXT: [[EXT:%.*]] = sext i16 [[TMP3]] to i32311; OPT-NEXT: store i32 [[EXT]], ptr addrspace(1) [[OUT:%.*]], align 4312; OPT-NEXT: ret void313;314 %ld = load i16, ptr addrspace(4) %in, align 4, !invariant.load !6315 %ext = sext i16 %ld to i32316 store i32 %ext, ptr addrspace(1) %out317 ret void318}319 320attributes #0 = { nounwind }321 322; OPT: !0 = !{i32 5, i32 0}323; OPT: !1 = !{i32 8, i32 0}324; OPT: !2 = !{i32 65520, i32 0}325; OPT: !3 = !{}326 327!0 = !{i16 5, i16 500}328!1 = !{i16 5, i16 -1}329!2 = !{i16 8, i16 12, i16 42, i16 99}330!3 = !{i16 0, i16 255}331!4 = !{i16 -16, i16 16}332!5 = !{i16 -16, i16 0}333!6 = !{}334