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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s --check-prefix=GFX123 4define amdgpu_ps void @test_wmma_f32_16x16x16_f16_imm(<8 x half> %A, <8 x half> %B, ptr addrspace(1) %out) {5; GFX12-LABEL: test_wmma_f32_16x16x16_f16_imm:6; GFX12: ; %bb.0: ; %bb7; GFX12-NEXT: v_wmma_f32_16x16x16_f16 v[10:17], v[0:3], v[4:7], 1.08; GFX12-NEXT: s_clause 0x19; GFX12-NEXT: global_store_b128 v[8:9], v[14:17], off offset:1610; GFX12-NEXT: global_store_b128 v[8:9], v[10:13], off11; GFX12-NEXT: s_endpgm12bb:13 %res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.f16.v8f32.v8f16(<8 x half> %A, <8 x half> %B, <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>)14 store <8 x float> %res, ptr addrspace(1) %out15 ret void16}17 18define amdgpu_ps void @test_wmma_f32_16x16x16_f16_imm_non_inlineable(<8 x half> %A, <8 x half> %B, ptr addrspace(1) %out) {19; GFX12-LABEL: test_wmma_f32_16x16x16_f16_imm_non_inlineable:20; GFX12: ; %bb.0: ; %bb21; GFX12-NEXT: v_mov_b32_e32 v10, 0x4040000022; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)23; GFX12-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v12, v1024; GFX12-NEXT: v_dual_mov_b32 v13, v10 :: v_dual_mov_b32 v14, v1025; GFX12-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v16, v1026; GFX12-NEXT: v_mov_b32_e32 v17, v1027; GFX12-NEXT: v_wmma_f32_16x16x16_f16 v[10:17], v[0:3], v[4:7], v[10:17]28; GFX12-NEXT: s_clause 0x129; GFX12-NEXT: global_store_b128 v[8:9], v[14:17], off offset:1630; GFX12-NEXT: global_store_b128 v[8:9], v[10:13], off31; GFX12-NEXT: s_endpgm32bb:33 %res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.f16.v8f32.v8f16(<8 x half> %A, <8 x half> %B, <8 x float> <float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0>)34 store <8 x float> %res, ptr addrspace(1) %out35 ret void36}37 38define amdgpu_ps void @test_wmma_f32_16x16x16_bf16_imm(<8 x i16> %A, <8 x i16> %B, ptr addrspace(1) %out) {39; GFX12-LABEL: test_wmma_f32_16x16x16_bf16_imm:40; GFX12: ; %bb.0: ; %bb41; GFX12-NEXT: v_wmma_f32_16x16x16_bf16 v[10:17], v[0:3], v[4:7], 1.042; GFX12-NEXT: s_clause 0x143; GFX12-NEXT: global_store_b128 v[8:9], v[14:17], off offset:1644; GFX12-NEXT: global_store_b128 v[8:9], v[10:13], off45; GFX12-NEXT: s_endpgm46bb:47 %res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf16.v8f32.v8i16(<8 x i16> %A, <8 x i16> %B, <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>)48 store <8 x float> %res, ptr addrspace(1) %out49 ret void50}51 52define amdgpu_ps void @test_wmma_f32_16x16x16_bf16_imm_non_inlineable(<8 x i16> %A, <8 x i16> %B, ptr addrspace(1) %out) {53; GFX12-LABEL: test_wmma_f32_16x16x16_bf16_imm_non_inlineable:54; GFX12: ; %bb.0: ; %bb55; GFX12-NEXT: v_mov_b32_e32 v10, 0x4040000056; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)57; GFX12-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v12, v1058; GFX12-NEXT: v_dual_mov_b32 v13, v10 :: v_dual_mov_b32 v14, v1059; GFX12-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v16, v1060; GFX12-NEXT: v_mov_b32_e32 v17, v1061; GFX12-NEXT: v_wmma_f32_16x16x16_bf16 v[10:17], v[0:3], v[4:7], v[10:17]62; GFX12-NEXT: s_clause 0x163; GFX12-NEXT: global_store_b128 v[8:9], v[14:17], off offset:1664; GFX12-NEXT: global_store_b128 v[8:9], v[10:13], off65; GFX12-NEXT: s_endpgm66bb:67 %res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf16.v8f32.v8i16(<8 x i16> %A, <8 x i16> %B, <8 x float> <float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0>)68 store <8 x float> %res, ptr addrspace(1) %out69 ret void70}71 72define amdgpu_ps void @test_wmma_f16_16x16x16_f16_imm(<8 x half> %A, <8 x half> %B, ptr addrspace(1) %out) {73; GFX12-LABEL: test_wmma_f16_16x16x16_f16_imm:74; GFX12: ; %bb.0: ; %bb75; GFX12-NEXT: v_wmma_f16_16x16x16_f16 v[10:13], v[0:3], v[4:7], 1.076; GFX12-NEXT: global_store_b128 v[8:9], v[10:13], off77; GFX12-NEXT: s_endpgm78bb:79 %res = call <8 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v8f16.v8f16(<8 x half> %A, <8 x half> %B, <8 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>, i1 0)80 store <8 x half> %res, ptr addrspace(1) %out81 ret void82}83 84define amdgpu_ps void @test_wmma_f16_16x16x16_f16_imm_non_inlineable(<8 x half> %A, <8 x half> %B, ptr addrspace(1) %out) {85; GFX12-LABEL: test_wmma_f16_16x16x16_f16_imm_non_inlineable:86; GFX12: ; %bb.0: ; %bb87; GFX12-NEXT: v_mov_b32_e32 v10, 0x4200420088; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)89; GFX12-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v12, v1090; GFX12-NEXT: v_mov_b32_e32 v13, v1091; GFX12-NEXT: v_wmma_f16_16x16x16_f16 v[10:13], v[0:3], v[4:7], v[10:13]92; GFX12-NEXT: global_store_b128 v[8:9], v[10:13], off93; GFX12-NEXT: s_endpgm94bb:95 %res = call <8 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v8f16.v8f16(<8 x half> %A, <8 x half> %B, <8 x half> <half 3.0, half 3.0, half 3.0, half 3.0, half 3.0, half 3.0, half 3.0, half 3.0>, i1 0)96 store <8 x half> %res, ptr addrspace(1) %out97 ret void98}99 100define amdgpu_ps void @test_wmma_bf16_16x16x16_bf16_imm(<8 x i16> %A, <8 x i16> %B, ptr addrspace(1) %out) {101; GFX12-LABEL: test_wmma_bf16_16x16x16_bf16_imm:102; GFX12: ; %bb.0: ; %bb103; GFX12-NEXT: v_mov_b32_e32 v10, 0x3f803f80104; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)105; GFX12-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v12, v10106; GFX12-NEXT: v_mov_b32_e32 v13, v10107; GFX12-NEXT: v_wmma_bf16_16x16x16_bf16 v[10:13], v[0:3], v[4:7], v[10:13]108; GFX12-NEXT: global_store_b128 v[8:9], v[10:13], off109; GFX12-NEXT: s_endpgm110bb:111 %res = call <8 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v8i16.v8i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> <i16 16256, i16 16256, i16 16256, i16 16256, i16 16256, i16 16256, i16 16256, i16 16256>, i1 0)112 store <8 x i16> %res, ptr addrspace(1) %out113 ret void114}115 116define amdgpu_ps void @test_wmma_bf16_16x16x16_bf16_imm_non_inlineable(<8 x i16> %A, <8 x i16> %B, ptr addrspace(1) %out) {117; GFX12-LABEL: test_wmma_bf16_16x16x16_bf16_imm_non_inlineable:118; GFX12: ; %bb.0: ; %bb119; GFX12-NEXT: v_mov_b32_e32 v10, 0x3fc03fc0120; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)121; GFX12-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v12, v10122; GFX12-NEXT: v_mov_b32_e32 v13, v10123; GFX12-NEXT: v_wmma_bf16_16x16x16_bf16 v[10:13], v[0:3], v[4:7], v[10:13]124; GFX12-NEXT: global_store_b128 v[8:9], v[10:13], off125; GFX12-NEXT: s_endpgm126bb:127 %res = call <8 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v8i16.v8i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> <i16 16320, i16 16320, i16 16320, i16 16320, i16 16320, i16 16320, i16 16320, i16 16320>, i1 0)128 store <8 x i16> %res, ptr addrspace(1) %out129 ret void130}131 132define amdgpu_ps void @test_wmma_i32_16x16x16_iu8_imm(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {133; GFX12-LABEL: test_wmma_i32_16x16x16_iu8_imm:134; GFX12: ; %bb.0: ; %bb135; GFX12-NEXT: v_wmma_i32_16x16x16_iu8 v[6:13], v[0:1], v[2:3], 1136; GFX12-NEXT: s_clause 0x1137; GFX12-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16138; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off139; GFX12-NEXT: s_endpgm140bb:141 %res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v8i32.v2i32(i1 0, <2 x i32> %A, i1 0, <2 x i32> %B, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, i1 0)142 store <8 x i32> %res, ptr addrspace(1) %out143 ret void144}145 146define amdgpu_ps void @test_wmma_i32_16x16x16_iu8_imm_non_inlineable(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {147; GFX12-LABEL: test_wmma_i32_16x16x16_iu8_imm_non_inlineable:148; GFX12: ; %bb.0: ; %bb149; GFX12-NEXT: v_mov_b32_e32 v6, 0x80150; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)151; GFX12-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6152; GFX12-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6153; GFX12-NEXT: v_dual_mov_b32 v11, v6 :: v_dual_mov_b32 v12, v6154; GFX12-NEXT: v_mov_b32_e32 v13, v6155; GFX12-NEXT: v_wmma_i32_16x16x16_iu8 v[6:13], v[0:1], v[2:3], v[6:13]156; GFX12-NEXT: s_clause 0x1157; GFX12-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16158; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off159; GFX12-NEXT: s_endpgm160bb:161 %res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v8i32.v2i32(i1 0, <2 x i32> %A, i1 0, <2 x i32> %B, <8 x i32> <i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128>, i1 0)162 store <8 x i32> %res, ptr addrspace(1) %out163 ret void164}165 166define amdgpu_ps void @test_wmma_i32_16x16x16_iu4_imm(i32 %A, i32 %B, ptr addrspace(1) %out) {167; GFX12-LABEL: test_wmma_i32_16x16x16_iu4_imm:168; GFX12: ; %bb.0: ; %bb169; GFX12-NEXT: v_wmma_i32_16x16x16_iu4 v[4:11], v0, v1, 1170; GFX12-NEXT: s_clause 0x1171; GFX12-NEXT: global_store_b128 v[2:3], v[8:11], off offset:16172; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off173; GFX12-NEXT: s_endpgm174bb:175 %res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v8i32.i32(i1 0, i32 %A, i1 0, i32 %B, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, i1 0)176 store <8 x i32> %res, ptr addrspace(1) %out177 ret void178}179 180define amdgpu_ps void @test_wmma_i32_16x16x16_iu4_imm_non_inlineable(i32 %A, i32 %B, ptr addrspace(1) %out) {181; GFX12-LABEL: test_wmma_i32_16x16x16_iu4_imm_non_inlineable:182; GFX12: ; %bb.0: ; %bb183; GFX12-NEXT: v_mov_b32_e32 v4, 0x80184; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)185; GFX12-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v6, v4186; GFX12-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v4187; GFX12-NEXT: v_dual_mov_b32 v9, v4 :: v_dual_mov_b32 v10, v4188; GFX12-NEXT: v_mov_b32_e32 v11, v4189; GFX12-NEXT: v_wmma_i32_16x16x16_iu4 v[4:11], v0, v1, v[4:11]190; GFX12-NEXT: s_clause 0x1191; GFX12-NEXT: global_store_b128 v[2:3], v[8:11], off offset:16192; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off193; GFX12-NEXT: s_endpgm194bb:195 %res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v8i32.i32(i1 0, i32 %A, i1 0, i32 %B, <8 x i32> <i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128>, i1 0)196 store <8 x i32> %res, ptr addrspace(1) %out197 ret void198}199 200define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_fp8_imm(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {201; GFX12-LABEL: test_wmma_f32_16x16x16_fp8_fp8_imm:202; GFX12: ; %bb.0: ; %bb203; GFX12-NEXT: v_wmma_f32_16x16x16_fp8_fp8 v[6:13], v[0:1], v[2:3], 1.0204; GFX12-NEXT: s_clause 0x1205; GFX12-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16206; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off207; GFX12-NEXT: s_endpgm208bb:209 %res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.fp8.v8f32.v2i32(<2 x i32> %A, <2 x i32> %B, <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>)210 store <8 x float> %res, ptr addrspace(1) %out211 ret void212}213 214define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_fp8_imm_non_inlineable(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {215; GFX12-LABEL: test_wmma_f32_16x16x16_fp8_fp8_imm_non_inlineable:216; GFX12: ; %bb.0: ; %bb217; GFX12-NEXT: v_mov_b32_e32 v6, 0x40400000218; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)219; GFX12-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6220; GFX12-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6221; GFX12-NEXT: v_dual_mov_b32 v11, v6 :: v_dual_mov_b32 v12, v6222; GFX12-NEXT: v_mov_b32_e32 v13, v6223; GFX12-NEXT: v_wmma_f32_16x16x16_fp8_fp8 v[6:13], v[0:1], v[2:3], v[6:13]224; GFX12-NEXT: s_clause 0x1225; GFX12-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16226; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off227; GFX12-NEXT: s_endpgm228bb:229 %res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.fp8.v8f32.v2i32(<2 x i32> %A, <2 x i32> %B, <8 x float> <float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0>)230 store <8 x float> %res, ptr addrspace(1) %out231 ret void232}233 234define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_fp8_imm(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {235; GFX12-LABEL: test_wmma_f32_16x16x16_bf8_fp8_imm:236; GFX12: ; %bb.0: ; %bb237; GFX12-NEXT: v_wmma_f32_16x16x16_bf8_fp8 v[6:13], v[0:1], v[2:3], 1.0238; GFX12-NEXT: s_clause 0x1239; GFX12-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16240; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off241; GFX12-NEXT: s_endpgm242bb:243 %res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.fp8.v8f32.v2i32(<2 x i32> %A, <2 x i32> %B, <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>)244 store <8 x float> %res, ptr addrspace(1) %out245 ret void246}247 248define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_fp8_imm_non_inlineable(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {249; GFX12-LABEL: test_wmma_f32_16x16x16_bf8_fp8_imm_non_inlineable:250; GFX12: ; %bb.0: ; %bb251; GFX12-NEXT: v_mov_b32_e32 v6, 0x40400000252; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)253; GFX12-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6254; GFX12-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6255; GFX12-NEXT: v_dual_mov_b32 v11, v6 :: v_dual_mov_b32 v12, v6256; GFX12-NEXT: v_mov_b32_e32 v13, v6257; GFX12-NEXT: v_wmma_f32_16x16x16_bf8_fp8 v[6:13], v[0:1], v[2:3], v[6:13]258; GFX12-NEXT: s_clause 0x1259; GFX12-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16260; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off261; GFX12-NEXT: s_endpgm262bb:263 %res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.fp8.v8f32.v2i32(<2 x i32> %A, <2 x i32> %B, <8 x float> <float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0>)264 store <8 x float> %res, ptr addrspace(1) %out265 ret void266}267 268define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_bf8_imm(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {269; GFX12-LABEL: test_wmma_f32_16x16x16_fp8_bf8_imm:270; GFX12: ; %bb.0: ; %bb271; GFX12-NEXT: v_wmma_f32_16x16x16_fp8_bf8 v[6:13], v[0:1], v[2:3], 1.0272; GFX12-NEXT: s_clause 0x1273; GFX12-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16274; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off275; GFX12-NEXT: s_endpgm276bb:277 %res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.bf8.v8f32.v2i32(<2 x i32> %A, <2 x i32> %B, <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>)278 store <8 x float> %res, ptr addrspace(1) %out279 ret void280}281 282define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_bf8_imm_non_inlineable(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {283; GFX12-LABEL: test_wmma_f32_16x16x16_fp8_bf8_imm_non_inlineable:284; GFX12: ; %bb.0: ; %bb285; GFX12-NEXT: v_mov_b32_e32 v6, 0x40400000286; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)287; GFX12-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6288; GFX12-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6289; GFX12-NEXT: v_dual_mov_b32 v11, v6 :: v_dual_mov_b32 v12, v6290; GFX12-NEXT: v_mov_b32_e32 v13, v6291; GFX12-NEXT: v_wmma_f32_16x16x16_fp8_bf8 v[6:13], v[0:1], v[2:3], v[6:13]292; GFX12-NEXT: s_clause 0x1293; GFX12-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16294; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off295; GFX12-NEXT: s_endpgm296bb:297 %res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.bf8.v8f32.v2i32(<2 x i32> %A, <2 x i32> %B, <8 x float> <float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0>)298 store <8 x float> %res, ptr addrspace(1) %out299 ret void300}301 302define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_bf8_imm(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {303; GFX12-LABEL: test_wmma_f32_16x16x16_bf8_bf8_imm:304; GFX12: ; %bb.0: ; %bb305; GFX12-NEXT: v_wmma_f32_16x16x16_bf8_bf8 v[6:13], v[0:1], v[2:3], 1.0306; GFX12-NEXT: s_clause 0x1307; GFX12-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16308; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off309; GFX12-NEXT: s_endpgm310bb:311 %res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.bf8.v8f32.v2i32(<2 x i32> %A, <2 x i32> %B, <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>)312 store <8 x float> %res, ptr addrspace(1) %out313 ret void314}315 316define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_bf8_imm_non_inlineable(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {317; GFX12-LABEL: test_wmma_f32_16x16x16_bf8_bf8_imm_non_inlineable:318; GFX12: ; %bb.0: ; %bb319; GFX12-NEXT: v_mov_b32_e32 v6, 0x40400000320; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)321; GFX12-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6322; GFX12-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6323; GFX12-NEXT: v_dual_mov_b32 v11, v6 :: v_dual_mov_b32 v12, v6324; GFX12-NEXT: v_mov_b32_e32 v13, v6325; GFX12-NEXT: v_wmma_f32_16x16x16_bf8_bf8 v[6:13], v[0:1], v[2:3], v[6:13]326; GFX12-NEXT: s_clause 0x1327; GFX12-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16328; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off329; GFX12-NEXT: s_endpgm330bb:331 %res = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.bf8.v8f32.v2i32(<2 x i32> %A, <2 x i32> %B, <8 x float> <float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0, float 3.0>)332 store <8 x float> %res, ptr addrspace(1) %out333 ret void334}335 336define amdgpu_ps void @test_wmma_i32_16x16x32_iu4_imm(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {337; GFX12-LABEL: test_wmma_i32_16x16x32_iu4_imm:338; GFX12: ; %bb.0: ; %bb339; GFX12-NEXT: v_wmma_i32_16x16x32_iu4 v[6:13], v[0:1], v[2:3], 1340; GFX12-NEXT: s_clause 0x1341; GFX12-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16342; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off343; GFX12-NEXT: s_endpgm344bb:345 %res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x32.iu4.v8i32.v2i32(i1 0, <2 x i32> %A, i1 0, <2 x i32> %B, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, i1 0)346 store <8 x i32> %res, ptr addrspace(1) %out347 ret void348}349 350define amdgpu_ps void @test_wmma_i32_16x16x32_iu4_imm_non_inlineable(<2 x i32> %A, <2 x i32> %B, ptr addrspace(1) %out) {351; GFX12-LABEL: test_wmma_i32_16x16x32_iu4_imm_non_inlineable:352; GFX12: ; %bb.0: ; %bb353; GFX12-NEXT: v_mov_b32_e32 v6, 0x80354; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)355; GFX12-NEXT: v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6356; GFX12-NEXT: v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v6357; GFX12-NEXT: v_dual_mov_b32 v11, v6 :: v_dual_mov_b32 v12, v6358; GFX12-NEXT: v_mov_b32_e32 v13, v6359; GFX12-NEXT: v_wmma_i32_16x16x32_iu4 v[6:13], v[0:1], v[2:3], v[6:13]360; GFX12-NEXT: s_clause 0x1361; GFX12-NEXT: global_store_b128 v[4:5], v[10:13], off offset:16362; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off363; GFX12-NEXT: s_endpgm364bb:365 %res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x32.iu4.v8i32.v2i32(i1 0, <2 x i32> %A, i1 0, <2 x i32> %B, <8 x i32> <i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128>, i1 0)366 store <8 x i32> %res, ptr addrspace(1) %out367 ret void368}369 370declare <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.f16.v8f32.v8f16(<8 x half>, <8 x half>, <8 x float>)371declare <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf16.v8f32.v8i16(<8 x i16>, <8 x i16>, <8 x float>)372declare <8 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v8f16.v8f16(<8 x half>, <8 x half>, <8 x half>, i1 immarg)373declare <8 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v8i16.v8i16(<8 x i16>, <8 x i16>, <8 x i16>, i1 immarg)374declare <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v8i32.v2i32(i1 immarg, <2 x i32>, i1 immarg, <2 x i32>, <8 x i32>, i1 immarg)375declare <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v8i32.i32(i1 immarg, i32, i1 immarg, i32, <8 x i32>, i1 immarg)376declare <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.fp8.v8f32.v2i32(<2 x i32>, <2 x i32>, <8 x float>)377declare <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.bf8.v8f32.v2i32(<2 x i32>, <2 x i32>, <8 x float>)378declare <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.fp8.v8f32.v2i32(<2 x i32>, <2 x i32>, <8 x float>)379declare <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.bf8.v8f32.v2i32(<2 x i32>, <2 x i32>, <8 x float>)380declare <8 x i32> @llvm.amdgcn.wmma.i32.16x16x32.iu4.v8i32.v2i32(i1 immarg, <2 x i32>, i1 immarg, <2 x i32>, <8 x i32>, i1 immarg)381