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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s --check-prefix=GFX123 4define amdgpu_ps void @test_wmma_i32_16x16x16_iu8_zext_src0(<2 x i32> %A, <2 x i32> %B, <8 x i32> %C, ptr addrspace(1) %out) {5; GFX12-LABEL: test_wmma_i32_16x16x16_iu8_zext_src0:6; GFX12: ; %bb.0: ; %bb7; GFX12-NEXT: v_wmma_i32_16x16x16_iu8 v[4:11], v[0:1], v[2:3], v[4:11] neg_lo:[1,0,0]8; GFX12-NEXT: s_clause 0x19; GFX12-NEXT: global_store_b128 v[12:13], v[8:11], off offset:1610; GFX12-NEXT: global_store_b128 v[12:13], v[4:7], off11; GFX12-NEXT: s_endpgm12bb:13 %res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v8i32.v2i32(i1 1, <2 x i32> %A, i1 0, <2 x i32> %B, <8 x i32> %C, i1 0)14 store <8 x i32> %res, ptr addrspace(1) %out15 ret void16}17 18define amdgpu_ps void @test_wmma_i32_16x16x16_iu8_zext_src1(<2 x i32> %A, <2 x i32> %B, <8 x i32> %C, ptr addrspace(1) %out) {19; GFX12-LABEL: test_wmma_i32_16x16x16_iu8_zext_src1:20; GFX12: ; %bb.0: ; %bb21; GFX12-NEXT: v_wmma_i32_16x16x16_iu8 v[4:11], v[0:1], v[2:3], v[4:11] neg_lo:[0,1,0]22; GFX12-NEXT: s_clause 0x123; GFX12-NEXT: global_store_b128 v[12:13], v[8:11], off offset:1624; GFX12-NEXT: global_store_b128 v[12:13], v[4:7], off25; GFX12-NEXT: s_endpgm26bb:27 %res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v8i32.v2i32(i1 0, <2 x i32> %A, i1 1, <2 x i32> %B, <8 x i32> %C, i1 0)28 store <8 x i32> %res, ptr addrspace(1) %out29 ret void30}31 32define amdgpu_ps void @test_wmma_i32_16x16x16_iu8_clamp(<2 x i32> %A, <2 x i32> %B, <8 x i32> %C, ptr addrspace(1) %out) {33; GFX12-LABEL: test_wmma_i32_16x16x16_iu8_clamp:34; GFX12: ; %bb.0: ; %bb35; GFX12-NEXT: v_wmma_i32_16x16x16_iu8 v[4:11], v[0:1], v[2:3], v[4:11] clamp36; GFX12-NEXT: s_clause 0x137; GFX12-NEXT: global_store_b128 v[12:13], v[8:11], off offset:1638; GFX12-NEXT: global_store_b128 v[12:13], v[4:7], off39; GFX12-NEXT: s_endpgm40bb:41 %res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v8i32.v2i32(i1 0, <2 x i32> %A, i1 0, <2 x i32> %B, <8 x i32> %C, i1 1)42 store <8 x i32> %res, ptr addrspace(1) %out43 ret void44}45 46 47 48define amdgpu_ps void @test_wmma_i32_16x16x16_iu4_zext_src0(i32 %A, i32 %B, <8 x i32> %C, ptr addrspace(1) %out) {49; GFX12-LABEL: test_wmma_i32_16x16x16_iu4_zext_src0:50; GFX12: ; %bb.0: ; %bb51; GFX12-NEXT: v_wmma_i32_16x16x16_iu4 v[2:9], v0, v1, v[2:9] neg_lo:[1,0,0]52; GFX12-NEXT: s_clause 0x153; GFX12-NEXT: global_store_b128 v[10:11], v[6:9], off offset:1654; GFX12-NEXT: global_store_b128 v[10:11], v[2:5], off55; GFX12-NEXT: s_endpgm56bb:57 %res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v8i32.i32(i1 1, i32 %A, i1 0, i32 %B, <8 x i32> %C, i1 0)58 store <8 x i32> %res, ptr addrspace(1) %out59 ret void60}61 62define amdgpu_ps void @test_wmma_i32_16x16x16_iu4_zext_src1(i32 %A, i32 %B, <8 x i32> %C, ptr addrspace(1) %out) {63; GFX12-LABEL: test_wmma_i32_16x16x16_iu4_zext_src1:64; GFX12: ; %bb.0: ; %bb65; GFX12-NEXT: v_wmma_i32_16x16x16_iu4 v[2:9], v0, v1, v[2:9] neg_lo:[0,1,0]66; GFX12-NEXT: s_clause 0x167; GFX12-NEXT: global_store_b128 v[10:11], v[6:9], off offset:1668; GFX12-NEXT: global_store_b128 v[10:11], v[2:5], off69; GFX12-NEXT: s_endpgm70bb:71 %res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v8i32.i32(i1 0, i32 %A, i1 1, i32 %B, <8 x i32> %C, i1 0)72 store <8 x i32> %res, ptr addrspace(1) %out73 ret void74}75 76define amdgpu_ps void @test_wmma_i32_16x16x16_iu4_clamp(i32 %A, i32 %B, <8 x i32> %C, ptr addrspace(1) %out) {77; GFX12-LABEL: test_wmma_i32_16x16x16_iu4_clamp:78; GFX12: ; %bb.0: ; %bb79; GFX12-NEXT: v_wmma_i32_16x16x16_iu4 v[2:9], v0, v1, v[2:9] clamp80; GFX12-NEXT: s_clause 0x181; GFX12-NEXT: global_store_b128 v[10:11], v[6:9], off offset:1682; GFX12-NEXT: global_store_b128 v[10:11], v[2:5], off83; GFX12-NEXT: s_endpgm84bb:85 %res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v8i32.i32(i1 0, i32 %A, i1 0, i32 %B, <8 x i32> %C, i1 1)86 store <8 x i32> %res, ptr addrspace(1) %out87 ret void88}89 90 91 92define amdgpu_ps void @test_wmma_i32_16x16x32_iu4_zext_src0(<2 x i32> %A, <2 x i32> %B, <8 x i32> %C, ptr addrspace(1) %out) {93; GFX12-LABEL: test_wmma_i32_16x16x32_iu4_zext_src0:94; GFX12: ; %bb.0: ; %bb95; GFX12-NEXT: v_wmma_i32_16x16x32_iu4 v[4:11], v[0:1], v[2:3], v[4:11] neg_lo:[1,0,0]96; GFX12-NEXT: s_clause 0x197; GFX12-NEXT: global_store_b128 v[12:13], v[8:11], off offset:1698; GFX12-NEXT: global_store_b128 v[12:13], v[4:7], off99; GFX12-NEXT: s_endpgm100bb:101 %res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x32.iu4.v8i32.v2i32(i1 1, <2 x i32> %A, i1 0, <2 x i32> %B, <8 x i32> %C, i1 0)102 store <8 x i32> %res, ptr addrspace(1) %out103 ret void104}105 106define amdgpu_ps void @test_wmma_i32_16x16x32_iu4_zext_src1(<2 x i32> %A, <2 x i32> %B, <8 x i32> %C, ptr addrspace(1) %out) {107; GFX12-LABEL: test_wmma_i32_16x16x32_iu4_zext_src1:108; GFX12: ; %bb.0: ; %bb109; GFX12-NEXT: v_wmma_i32_16x16x32_iu4 v[4:11], v[0:1], v[2:3], v[4:11] neg_lo:[0,1,0]110; GFX12-NEXT: s_clause 0x1111; GFX12-NEXT: global_store_b128 v[12:13], v[8:11], off offset:16112; GFX12-NEXT: global_store_b128 v[12:13], v[4:7], off113; GFX12-NEXT: s_endpgm114bb:115 %res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x32.iu4.v8i32.v2i32(i1 0, <2 x i32> %A, i1 1, <2 x i32> %B, <8 x i32> %C, i1 0)116 store <8 x i32> %res, ptr addrspace(1) %out117 ret void118}119 120define amdgpu_ps void @test_wmma_i32_16x16x32_iu4_clamp(<2 x i32> %A, <2 x i32> %B, <8 x i32> %C, ptr addrspace(1) %out) {121; GFX12-LABEL: test_wmma_i32_16x16x32_iu4_clamp:122; GFX12: ; %bb.0: ; %bb123; GFX12-NEXT: v_wmma_i32_16x16x32_iu4 v[4:11], v[0:1], v[2:3], v[4:11] clamp124; GFX12-NEXT: s_clause 0x1125; GFX12-NEXT: global_store_b128 v[12:13], v[8:11], off offset:16126; GFX12-NEXT: global_store_b128 v[12:13], v[4:7], off127; GFX12-NEXT: s_endpgm128bb:129 %res = call <8 x i32> @llvm.amdgcn.wmma.i32.16x16x32.iu4.v8i32.v2i32(i1 0, <2 x i32> %A, i1 0, <2 x i32> %B, <8 x i32> %C, i1 1)130 store <8 x i32> %res, ptr addrspace(1) %out131 ret void132}133 134 135 136 137 138define amdgpu_ps void @test_swmmac_i32_16x16x32_iu8_zext_src0(<2 x i32> %A, <4 x i32> %B, <8 x i32> %C, i16 %Index, ptr addrspace(1) %out) {139; GFX12-LABEL: test_swmmac_i32_16x16x32_iu8_zext_src0:140; GFX12: ; %bb.0: ; %bb141; GFX12-NEXT: v_swmmac_i32_16x16x32_iu8 v[6:13], v[0:1], v[2:5], v14 neg_lo:[1,0,0]142; GFX12-NEXT: s_clause 0x1143; GFX12-NEXT: global_store_b128 v[15:16], v[10:13], off offset:16144; GFX12-NEXT: global_store_b128 v[15:16], v[6:9], off145; GFX12-NEXT: s_endpgm146bb:147 %res = call <8 x i32> @llvm.amdgcn.swmmac.i32.16x16x32.iu8.v8i32.v2i32.v4i32.i16(i1 1, <2 x i32> %A, i1 0, <4 x i32> %B, <8 x i32> %C, i16 %Index, i1 0)148 store <8 x i32> %res, ptr addrspace(1) %out149 ret void150}151 152define amdgpu_ps void @test_swmmac_i32_16x16x32_iu8_zext_src1(<2 x i32> %A, <4 x i32> %B, <8 x i32> %C, i16 %Index, ptr addrspace(1) %out) {153; GFX12-LABEL: test_swmmac_i32_16x16x32_iu8_zext_src1:154; GFX12: ; %bb.0: ; %bb155; GFX12-NEXT: v_swmmac_i32_16x16x32_iu8 v[6:13], v[0:1], v[2:5], v14 neg_lo:[0,1,0]156; GFX12-NEXT: s_clause 0x1157; GFX12-NEXT: global_store_b128 v[15:16], v[10:13], off offset:16158; GFX12-NEXT: global_store_b128 v[15:16], v[6:9], off159; GFX12-NEXT: s_endpgm160bb:161 %res = call <8 x i32> @llvm.amdgcn.swmmac.i32.16x16x32.iu8.v8i32.v2i32.v4i32.i16(i1 0, <2 x i32> %A, i1 1, <4 x i32> %B, <8 x i32> %C, i16 %Index, i1 0)162 store <8 x i32> %res, ptr addrspace(1) %out163 ret void164}165 166define amdgpu_ps void @test_swmmac_i32_16x16x32_iu8_clamp(<2 x i32> %A, <4 x i32> %B, <8 x i32> %C, i16 %Index, ptr addrspace(1) %out) {167; GFX12-LABEL: test_swmmac_i32_16x16x32_iu8_clamp:168; GFX12: ; %bb.0: ; %bb169; GFX12-NEXT: v_swmmac_i32_16x16x32_iu8 v[6:13], v[0:1], v[2:5], v14 clamp170; GFX12-NEXT: s_clause 0x1171; GFX12-NEXT: global_store_b128 v[15:16], v[10:13], off offset:16172; GFX12-NEXT: global_store_b128 v[15:16], v[6:9], off173; GFX12-NEXT: s_endpgm174bb:175 %res = call <8 x i32> @llvm.amdgcn.swmmac.i32.16x16x32.iu8.v8i32.v2i32.v4i32.i16(i1 0, <2 x i32> %A, i1 0, <4 x i32> %B, <8 x i32> %C, i16 %Index, i1 1)176 store <8 x i32> %res, ptr addrspace(1) %out177 ret void178}179 180 181 182define amdgpu_ps void @test_swmmac_i32_16x16x32_iu4_zext_src0(i32 %A, <2 x i32> %B, <8 x i32> %C, i16 %Index, ptr addrspace(1) %out) {183; GFX12-LABEL: test_swmmac_i32_16x16x32_iu4_zext_src0:184; GFX12: ; %bb.0: ; %bb185; GFX12-NEXT: v_swmmac_i32_16x16x32_iu4 v[3:10], v0, v[1:2], v11 neg_lo:[1,0,0]186; GFX12-NEXT: s_clause 0x1187; GFX12-NEXT: global_store_b128 v[12:13], v[7:10], off offset:16188; GFX12-NEXT: global_store_b128 v[12:13], v[3:6], off189; GFX12-NEXT: s_endpgm190bb:191 %res = call <8 x i32> @llvm.amdgcn.swmmac.i32.16x16x32.iu4.v8i32.i32.v2i32.i16(i1 1, i32 %A, i1 0, <2 x i32> %B, <8 x i32> %C, i16 %Index, i1 0)192 store <8 x i32> %res, ptr addrspace(1) %out193 ret void194}195 196define amdgpu_ps void @test_swmmac_i32_16x16x32_iu4_zext_src1(i32 %A, <2 x i32> %B, <8 x i32> %C, i16 %Index, ptr addrspace(1) %out) {197; GFX12-LABEL: test_swmmac_i32_16x16x32_iu4_zext_src1:198; GFX12: ; %bb.0: ; %bb199; GFX12-NEXT: v_swmmac_i32_16x16x32_iu4 v[3:10], v0, v[1:2], v11 neg_lo:[0,1,0]200; GFX12-NEXT: s_clause 0x1201; GFX12-NEXT: global_store_b128 v[12:13], v[7:10], off offset:16202; GFX12-NEXT: global_store_b128 v[12:13], v[3:6], off203; GFX12-NEXT: s_endpgm204bb:205 %res = call <8 x i32> @llvm.amdgcn.swmmac.i32.16x16x32.iu4.v8i32.i32.v2i32.i16(i1 0, i32 %A, i1 1, <2 x i32> %B, <8 x i32> %C, i16 %Index, i1 0)206 store <8 x i32> %res, ptr addrspace(1) %out207 ret void208}209 210define amdgpu_ps void @test_swmmac_i32_16x16x32_iu4_clamp(i32 %A, <2 x i32> %B, <8 x i32> %C, i16 %Index, ptr addrspace(1) %out) {211; GFX12-LABEL: test_swmmac_i32_16x16x32_iu4_clamp:212; GFX12: ; %bb.0: ; %bb213; GFX12-NEXT: v_swmmac_i32_16x16x32_iu4 v[3:10], v0, v[1:2], v11 clamp214; GFX12-NEXT: s_clause 0x1215; GFX12-NEXT: global_store_b128 v[12:13], v[7:10], off offset:16216; GFX12-NEXT: global_store_b128 v[12:13], v[3:6], off217; GFX12-NEXT: s_endpgm218bb:219 %res = call <8 x i32> @llvm.amdgcn.swmmac.i32.16x16x32.iu4.v8i32.i32.v2i32.i16(i1 0, i32 %A, i1 0, <2 x i32> %B, <8 x i32> %C, i16 %Index, i1 1)220 store <8 x i32> %res, ptr addrspace(1) %out221 ret void222}223 224 225 226define amdgpu_ps void @test_swmmac_i32_16x16x64_iu4_zext_src0(<2 x i32> %A, <4 x i32> %B, <8 x i32> %C, i32 %Index, ptr addrspace(1) %out) {227; GFX12-LABEL: test_swmmac_i32_16x16x64_iu4_zext_src0:228; GFX12: ; %bb.0: ; %bb229; GFX12-NEXT: v_swmmac_i32_16x16x64_iu4 v[6:13], v[0:1], v[2:5], v14 neg_lo:[1,0,0]230; GFX12-NEXT: s_clause 0x1231; GFX12-NEXT: global_store_b128 v[15:16], v[10:13], off offset:16232; GFX12-NEXT: global_store_b128 v[15:16], v[6:9], off233; GFX12-NEXT: s_endpgm234bb:235 %res = call <8 x i32> @llvm.amdgcn.swmmac.i32.16x16x64.iu4.v8i32.v2i32.v4i32.i32(i1 1, <2 x i32> %A, i1 0, <4 x i32> %B, <8 x i32> %C, i32 %Index, i1 0)236 store <8 x i32> %res, ptr addrspace(1) %out237 ret void238}239 240define amdgpu_ps void @test_swmmac_i32_16x16x64_iu4_zext_src1(<2 x i32> %A, <4 x i32> %B, <8 x i32> %C, i32 %Index, ptr addrspace(1) %out) {241; GFX12-LABEL: test_swmmac_i32_16x16x64_iu4_zext_src1:242; GFX12: ; %bb.0: ; %bb243; GFX12-NEXT: v_swmmac_i32_16x16x64_iu4 v[6:13], v[0:1], v[2:5], v14 neg_lo:[0,1,0]244; GFX12-NEXT: s_clause 0x1245; GFX12-NEXT: global_store_b128 v[15:16], v[10:13], off offset:16246; GFX12-NEXT: global_store_b128 v[15:16], v[6:9], off247; GFX12-NEXT: s_endpgm248bb:249 %res = call <8 x i32> @llvm.amdgcn.swmmac.i32.16x16x64.iu4.v8i32.v2i32.v4i32.i32(i1 0, <2 x i32> %A, i1 1, <4 x i32> %B, <8 x i32> %C, i32 %Index, i1 0)250 store <8 x i32> %res, ptr addrspace(1) %out251 ret void252}253 254define amdgpu_ps void @test_swmmac_i32_16x16x64_iu4_clamp(<2 x i32> %A, <4 x i32> %B, <8 x i32> %C, i32 %Index, ptr addrspace(1) %out) {255; GFX12-LABEL: test_swmmac_i32_16x16x64_iu4_clamp:256; GFX12: ; %bb.0: ; %bb257; GFX12-NEXT: v_swmmac_i32_16x16x64_iu4 v[6:13], v[0:1], v[2:5], v14 clamp258; GFX12-NEXT: s_clause 0x1259; GFX12-NEXT: global_store_b128 v[15:16], v[10:13], off offset:16260; GFX12-NEXT: global_store_b128 v[15:16], v[6:9], off261; GFX12-NEXT: s_endpgm262bb:263 %res = call <8 x i32> @llvm.amdgcn.swmmac.i32.16x16x64.iu4.v8i32.v2i32.v4i32.i32(i1 0, <2 x i32> %A, i1 0, <4 x i32> %B, <8 x i32> %C, i32 %Index, i1 1)264 store <8 x i32> %res, ptr addrspace(1) %out265 ret void266}267 268declare <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v8i32.v2i32(i1 immarg, <2 x i32>, i1 immarg, <2 x i32>, <8 x i32>, i1 immarg)269declare <8 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v8i32.i32(i1 immarg, i32, i1 immarg, i32, <8 x i32>, i1 immarg)270declare <8 x i32> @llvm.amdgcn.wmma.i32.16x16x32.iu4.v8i32.v2i32(i1 immarg, <2 x i32>, i1 immarg, <2 x i32>, <8 x i32>, i1 immarg)271declare <8 x i32> @llvm.amdgcn.swmmac.i32.16x16x32.iu8.v8i32.v2i32.v4i32.i16(i1 immarg, <2 x i32>, i1 immarg, <4 x i32>, <8 x i32>, i16 %Index, i1 immarg)272declare <8 x i32> @llvm.amdgcn.swmmac.i32.16x16x32.iu4.v8i32.i32.v2i32.i16(i1 immarg, i32, i1 immarg, <2 x i32>, <8 x i32>, i16 %Index, i1 immarg)273declare <8 x i32> @llvm.amdgcn.swmmac.i32.16x16x64.iu4.v8i32.v2i32.v4i32.i32(i1 immarg, <2 x i32>, i1 immarg, <4 x i32>, <8 x i32>, i32 %Index, i1 immarg)274