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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck %s --check-prefix=GFX123 4define amdgpu_ps void @test_wmma_f32_16x16x16_f16_imm(<4 x half> %A, <4 x half> %B, ptr addrspace(1) %out) {5; GFX12-LABEL: test_wmma_f32_16x16x16_f16_imm:6; GFX12: ; %bb.0: ; %bb7; GFX12-NEXT: v_wmma_f32_16x16x16_f16 v[6:9], v[0:1], v[2:3], 1.08; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off9; GFX12-NEXT: s_endpgm10bb:11 %res = call <4 x float>@llvm.amdgcn.wmma.f32.16x16x16.f16.v4f32.v4f16(<4 x half> %A, <4 x half> %B, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)12 store <4 x float> %res, ptr addrspace(1) %out13 ret void14}15 16define amdgpu_ps void @test_wmma_f32_16x16x16_f16_imm_non_inlineable(<4 x half> %A, <4 x half> %B, ptr addrspace(1) %out) {17; GFX12-LABEL: test_wmma_f32_16x16x16_f16_imm_non_inlineable:18; GFX12: ; %bb.0: ; %bb19; GFX12-NEXT: v_mov_b32_e32 v6, 0x4040000020; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)21; GFX12-NEXT: v_mov_b32_e32 v7, v622; GFX12-NEXT: v_mov_b32_e32 v8, v623; GFX12-NEXT: v_mov_b32_e32 v9, v624; GFX12-NEXT: v_wmma_f32_16x16x16_f16 v[6:9], v[0:1], v[2:3], v[6:9]25; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off26; GFX12-NEXT: s_endpgm27bb:28 %res = call <4 x float>@llvm.amdgcn.wmma.f32.16x16x16.f16.v4f32.v4f16(<4 x half> %A, <4 x half> %B, <4 x float> <float 3.0, float 3.0, float 3.0, float 3.0>)29 store <4 x float> %res, ptr addrspace(1) %out30 ret void31}32 33define amdgpu_ps void @test_wmma_f32_16x16x16_bf16_imm(<4 x i16> %A, <4 x i16> %B, ptr addrspace(1) %out) {34; GFX12-LABEL: test_wmma_f32_16x16x16_bf16_imm:35; GFX12: ; %bb.0: ; %bb36; GFX12-NEXT: v_wmma_f32_16x16x16_bf16 v[6:9], v[0:1], v[2:3], 1.037; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off38; GFX12-NEXT: s_endpgm39bb:40 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf16.v4f32.v4i16(<4 x i16> %A, <4 x i16> %B, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)41 store <4 x float> %res, ptr addrspace(1) %out42 ret void43}44 45define amdgpu_ps void @test_wmma_f32_16x16x16_bf16_imm_non_inlineable(<4 x i16> %A, <4 x i16> %B, ptr addrspace(1) %out) {46; GFX12-LABEL: test_wmma_f32_16x16x16_bf16_imm_non_inlineable:47; GFX12: ; %bb.0: ; %bb48; GFX12-NEXT: v_mov_b32_e32 v6, 0x4040000049; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)50; GFX12-NEXT: v_mov_b32_e32 v7, v651; GFX12-NEXT: v_mov_b32_e32 v8, v652; GFX12-NEXT: v_mov_b32_e32 v9, v653; GFX12-NEXT: v_wmma_f32_16x16x16_bf16 v[6:9], v[0:1], v[2:3], v[6:9]54; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off55; GFX12-NEXT: s_endpgm56bb:57 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf16.v4f32.v4i16(<4 x i16> %A, <4 x i16> %B, <4 x float> <float 3.0, float 3.0, float 3.0, float 3.0>)58 store <4 x float> %res, ptr addrspace(1) %out59 ret void60}61 62define amdgpu_ps void @test_wmma_f16_16x16x16_f16_imm(<4 x half> %A, <4 x half> %B, ptr addrspace(1) %out) {63; GFX12-LABEL: test_wmma_f16_16x16x16_f16_imm:64; GFX12: ; %bb.0: ; %bb65; GFX12-NEXT: v_wmma_f16_16x16x16_f16 v[6:7], v[0:1], v[2:3], 1.066; GFX12-NEXT: global_store_b64 v[4:5], v[6:7], off67; GFX12-NEXT: s_endpgm68bb:69 %res = call <4 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v4f16.v4f16(<4 x half> %A, <4 x half> %B, <4 x half> <half 1.0, half 1.0, half 1.0, half 1.0>, i1 0)70 store <4 x half> %res, ptr addrspace(1) %out71 ret void72}73 74define amdgpu_ps void @test_wmma_f16_16x16x16_f16_imm_non_inlineable(<4 x half> %A, <4 x half> %B, ptr addrspace(1) %out) {75; GFX12-LABEL: test_wmma_f16_16x16x16_f16_imm_non_inlineable:76; GFX12: ; %bb.0: ; %bb77; GFX12-NEXT: v_mov_b32_e32 v6, 0x4200420078; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)79; GFX12-NEXT: v_mov_b32_e32 v7, v680; GFX12-NEXT: v_wmma_f16_16x16x16_f16 v[6:7], v[0:1], v[2:3], v[6:7]81; GFX12-NEXT: global_store_b64 v[4:5], v[6:7], off82; GFX12-NEXT: s_endpgm83bb:84 %res = call <4 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v4f16.v4f16(<4 x half> %A, <4 x half> %B, <4 x half> <half 3.0, half 3.0, half 3.0, half 3.0>, i1 0)85 store <4 x half> %res, ptr addrspace(1) %out86 ret void87}88 89define amdgpu_ps void @test_wmma_bf16_16x16x16_bf16_imm(<4 x i16> %A, <4 x i16> %B, ptr addrspace(1) %out) {90; GFX12-LABEL: test_wmma_bf16_16x16x16_bf16_imm:91; GFX12: ; %bb.0: ; %bb92; GFX12-NEXT: v_mov_b32_e32 v6, 0x3f803f8093; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)94; GFX12-NEXT: v_mov_b32_e32 v7, v695; GFX12-NEXT: v_wmma_bf16_16x16x16_bf16 v[6:7], v[0:1], v[2:3], v[6:7]96; GFX12-NEXT: global_store_b64 v[4:5], v[6:7], off97; GFX12-NEXT: s_endpgm98bb:99 %res = call <4 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v4i16.v4i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> <i16 16256, i16 16256, i16 16256, i16 16256>, i1 0)100 store <4 x i16> %res, ptr addrspace(1) %out101 ret void102}103 104define amdgpu_ps void @test_wmma_bf16_16x16x16_bf16_imm_non_inlineable(<4 x i16> %A, <4 x i16> %B, ptr addrspace(1) %out) {105; GFX12-LABEL: test_wmma_bf16_16x16x16_bf16_imm_non_inlineable:106; GFX12: ; %bb.0: ; %bb107; GFX12-NEXT: v_mov_b32_e32 v6, 0x3fc03fc0108; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)109; GFX12-NEXT: v_mov_b32_e32 v7, v6110; GFX12-NEXT: v_wmma_bf16_16x16x16_bf16 v[6:7], v[0:1], v[2:3], v[6:7]111; GFX12-NEXT: global_store_b64 v[4:5], v[6:7], off112; GFX12-NEXT: s_endpgm113bb:114 %res = call <4 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v4i16.v4i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> <i16 16320, i16 16320, i16 16320, i16 16320>, i1 0)115 store <4 x i16> %res, ptr addrspace(1) %out116 ret void117}118 119define amdgpu_ps void @test_wmma_i32_16x16x16_iu8_imm(i32 %A, i32 %B, ptr addrspace(1) %out) {120; GFX12-LABEL: test_wmma_i32_16x16x16_iu8_imm:121; GFX12: ; %bb.0: ; %bb122; GFX12-NEXT: v_wmma_i32_16x16x16_iu8 v[4:7], v0, v1, 1123; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off124; GFX12-NEXT: s_endpgm125bb:126 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.i32(i1 0, i32 %A, i1 0, i32 %B, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, i1 0)127 store <4 x i32> %res, ptr addrspace(1) %out128 ret void129}130 131define amdgpu_ps void @test_wmma_i32_16x16x16_iu8_imm_non_inlineable(i32 %A, i32 %B, ptr addrspace(1) %out) {132; GFX12-LABEL: test_wmma_i32_16x16x16_iu8_imm_non_inlineable:133; GFX12: ; %bb.0: ; %bb134; GFX12-NEXT: v_mov_b32_e32 v4, 0x80135; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)136; GFX12-NEXT: v_mov_b32_e32 v5, v4137; GFX12-NEXT: v_mov_b32_e32 v6, v4138; GFX12-NEXT: v_mov_b32_e32 v7, v4139; GFX12-NEXT: v_wmma_i32_16x16x16_iu8 v[4:7], v0, v1, v[4:7]140; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off141; GFX12-NEXT: s_endpgm142bb:143 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.i32(i1 0, i32 %A, i1 0, i32 %B, <4 x i32> <i32 128, i32 128, i32 128, i32 128>, i1 0)144 store <4 x i32> %res, ptr addrspace(1) %out145 ret void146}147 148define amdgpu_ps void @test_wmma_i32_16x16x16_iu4_imm(i32 %A, i32 %B, ptr addrspace(1) %out) {149; GFX12-LABEL: test_wmma_i32_16x16x16_iu4_imm:150; GFX12: ; %bb.0: ; %bb151; GFX12-NEXT: v_wmma_i32_16x16x16_iu4 v[4:7], v0, v1, 1152; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off153; GFX12-NEXT: s_endpgm154bb:155 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.i32(i1 0, i32 %A, i1 0, i32 %B, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, i1 0)156 store <4 x i32> %res, ptr addrspace(1) %out157 ret void158}159 160define amdgpu_ps void @test_wmma_i32_16x16x16_iu4_imm_non_inlineable(i32 %A, i32 %B, ptr addrspace(1) %out) {161; GFX12-LABEL: test_wmma_i32_16x16x16_iu4_imm_non_inlineable:162; GFX12: ; %bb.0: ; %bb163; GFX12-NEXT: v_mov_b32_e32 v4, 0x80164; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)165; GFX12-NEXT: v_mov_b32_e32 v5, v4166; GFX12-NEXT: v_mov_b32_e32 v6, v4167; GFX12-NEXT: v_mov_b32_e32 v7, v4168; GFX12-NEXT: v_wmma_i32_16x16x16_iu4 v[4:7], v0, v1, v[4:7]169; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off170; GFX12-NEXT: s_endpgm171bb:172 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.i32(i1 0, i32 %A, i1 0, i32 %B, <4 x i32> <i32 128, i32 128, i32 128, i32 128>, i1 0)173 store <4 x i32> %res, ptr addrspace(1) %out174 ret void175}176 177define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_fp8_imm(i32 %A, i32 %B, <4 x float> %C, ptr addrspace(1) %out) {178; GFX12-LABEL: test_wmma_f32_16x16x16_fp8_fp8_imm:179; GFX12: ; %bb.0: ; %bb180; GFX12-NEXT: v_wmma_f32_16x16x16_fp8_fp8 v[4:7], v0, v1, 1.0181; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off182; GFX12-NEXT: s_endpgm183bb:184 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.fp8.v4f32.i32(i32 %A, i32 %B, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)185 store <4 x float> %res, ptr addrspace(1) %out186 ret void187}188 189define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_fp8_imm_non_inlineable(i32 %A, i32 %B, <4 x float> %C, ptr addrspace(1) %out) {190; GFX12-LABEL: test_wmma_f32_16x16x16_fp8_fp8_imm_non_inlineable:191; GFX12: ; %bb.0: ; %bb192; GFX12-NEXT: v_mov_b32_e32 v4, 0x40400000193; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)194; GFX12-NEXT: v_mov_b32_e32 v5, v4195; GFX12-NEXT: v_mov_b32_e32 v6, v4196; GFX12-NEXT: v_mov_b32_e32 v7, v4197; GFX12-NEXT: v_wmma_f32_16x16x16_fp8_fp8 v[4:7], v0, v1, v[4:7]198; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off199; GFX12-NEXT: s_endpgm200bb:201 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.fp8.v4f32.i32(i32 %A, i32 %B, <4 x float> <float 3.0, float 3.0, float 3.0, float 3.0>)202 store <4 x float> %res, ptr addrspace(1) %out203 ret void204}205 206define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_fp8_imm(i32 %A, i32 %B, <4 x float> %C, ptr addrspace(1) %out) {207; GFX12-LABEL: test_wmma_f32_16x16x16_bf8_fp8_imm:208; GFX12: ; %bb.0: ; %bb209; GFX12-NEXT: v_wmma_f32_16x16x16_bf8_fp8 v[4:7], v0, v1, 1.0210; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off211; GFX12-NEXT: s_endpgm212bb:213 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.fp8.v4f32.i32(i32 %A, i32 %B, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)214 store <4 x float> %res, ptr addrspace(1) %out215 ret void216}217 218define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_fp8_imm_non_inlineable(i32 %A, i32 %B, <4 x float> %C, ptr addrspace(1) %out) {219; GFX12-LABEL: test_wmma_f32_16x16x16_bf8_fp8_imm_non_inlineable:220; GFX12: ; %bb.0: ; %bb221; GFX12-NEXT: v_mov_b32_e32 v4, 0x40400000222; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)223; GFX12-NEXT: v_mov_b32_e32 v5, v4224; GFX12-NEXT: v_mov_b32_e32 v6, v4225; GFX12-NEXT: v_mov_b32_e32 v7, v4226; GFX12-NEXT: v_wmma_f32_16x16x16_bf8_fp8 v[4:7], v0, v1, v[4:7]227; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off228; GFX12-NEXT: s_endpgm229bb:230 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.fp8.v4f32.i32(i32 %A, i32 %B, <4 x float> <float 3.0, float 3.0, float 3.0, float 3.0>)231 store <4 x float> %res, ptr addrspace(1) %out232 ret void233}234 235define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_bf8_imm(i32 %A, i32 %B, <4 x float> %C, ptr addrspace(1) %out) {236; GFX12-LABEL: test_wmma_f32_16x16x16_fp8_bf8_imm:237; GFX12: ; %bb.0: ; %bb238; GFX12-NEXT: v_wmma_f32_16x16x16_fp8_bf8 v[4:7], v0, v1, 1.0239; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off240; GFX12-NEXT: s_endpgm241bb:242 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.bf8.v4f32.i32(i32 %A, i32 %B, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)243 store <4 x float> %res, ptr addrspace(1) %out244 ret void245}246 247define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_bf8_imm_non_inlineable(i32 %A, i32 %B, <4 x float> %C, ptr addrspace(1) %out) {248; GFX12-LABEL: test_wmma_f32_16x16x16_fp8_bf8_imm_non_inlineable:249; GFX12: ; %bb.0: ; %bb250; GFX12-NEXT: v_mov_b32_e32 v4, 0x40400000251; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)252; GFX12-NEXT: v_mov_b32_e32 v5, v4253; GFX12-NEXT: v_mov_b32_e32 v6, v4254; GFX12-NEXT: v_mov_b32_e32 v7, v4255; GFX12-NEXT: v_wmma_f32_16x16x16_fp8_bf8 v[4:7], v0, v1, v[4:7]256; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off257; GFX12-NEXT: s_endpgm258bb:259 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.bf8.v4f32.i32(i32 %A, i32 %B, <4 x float> <float 3.0, float 3.0, float 3.0, float 3.0>)260 store <4 x float> %res, ptr addrspace(1) %out261 ret void262}263 264define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_bf8_imm(i32 %A, i32 %B, <4 x float> %C, ptr addrspace(1) %out) {265; GFX12-LABEL: test_wmma_f32_16x16x16_bf8_bf8_imm:266; GFX12: ; %bb.0: ; %bb267; GFX12-NEXT: v_wmma_f32_16x16x16_bf8_bf8 v[4:7], v0, v1, 1.0268; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off269; GFX12-NEXT: s_endpgm270bb:271 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.bf8.v4f32.i32(i32 %A, i32 %B, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)272 store <4 x float> %res, ptr addrspace(1) %out273 ret void274}275 276define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_bf8_imm_non_inlineable(i32 %A, i32 %B, <4 x float> %C, ptr addrspace(1) %out) {277; GFX12-LABEL: test_wmma_f32_16x16x16_bf8_bf8_imm_non_inlineable:278; GFX12: ; %bb.0: ; %bb279; GFX12-NEXT: v_mov_b32_e32 v4, 0x40400000280; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)281; GFX12-NEXT: v_mov_b32_e32 v5, v4282; GFX12-NEXT: v_mov_b32_e32 v6, v4283; GFX12-NEXT: v_mov_b32_e32 v7, v4284; GFX12-NEXT: v_wmma_f32_16x16x16_bf8_bf8 v[4:7], v0, v1, v[4:7]285; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off286; GFX12-NEXT: s_endpgm287bb:288 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.bf8.v4f32.i32(i32 %A, i32 %B, <4 x float> <float 3.0, float 3.0, float 3.0, float 3.0>)289 store <4 x float> %res, ptr addrspace(1) %out290 ret void291}292 293define amdgpu_ps void @test_wmma_i32_16x16x32_iu4_imm(i32 %A, i32 %B, <4 x i32> %C, ptr addrspace(1) %out) {294; GFX12-LABEL: test_wmma_i32_16x16x32_iu4_imm:295; GFX12: ; %bb.0: ; %bb296; GFX12-NEXT: v_wmma_i32_16x16x32_iu4 v[4:7], v0, v1, 1297; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off298; GFX12-NEXT: s_endpgm299bb:300 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x32.iu4.v4i32.i32(i1 0, i32 %A, i1 0, i32 %B, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, i1 0)301 store <4 x i32> %res, ptr addrspace(1) %out302 ret void303}304 305define amdgpu_ps void @test_wmma_i32_16x16x32_iu4_imm_non_inlineable(i32 %A, i32 %B, <4 x i32> %C, ptr addrspace(1) %out) {306; GFX12-LABEL: test_wmma_i32_16x16x32_iu4_imm_non_inlineable:307; GFX12: ; %bb.0: ; %bb308; GFX12-NEXT: v_mov_b32_e32 v4, 0x80309; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)310; GFX12-NEXT: v_mov_b32_e32 v5, v4311; GFX12-NEXT: v_mov_b32_e32 v6, v4312; GFX12-NEXT: v_mov_b32_e32 v7, v4313; GFX12-NEXT: v_wmma_i32_16x16x32_iu4 v[4:7], v0, v1, v[4:7]314; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off315; GFX12-NEXT: s_endpgm316bb:317 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x32.iu4.v4i32.i32(i1 0, i32 %A, i1 0, i32 %B, <4 x i32> <i32 128, i32 128, i32 128, i32 128>, i1 0)318 store <4 x i32> %res, ptr addrspace(1) %out319 ret void320}321 322declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.f16.v4f32.v4f16(<4 x half>, <4 x half>, <4 x float>)323declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf16.v4f32.v4i16(<4 x i16>, <4 x i16>, <4 x float>)324declare <4 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v4f16.v4f16(<4 x half>, <4 x half>, <4 x half>, i1 immarg)325declare <4 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v4i16.v4i16(<4 x i16>, <4 x i16>, <4 x i16>, i1 immarg)326declare <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.i32(i1 immarg, i32, i1 immarg, i32, <4 x i32>, i1 immarg)327declare <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.i32(i1 immarg, i32, i1 immarg, i32, <4 x i32>, i1 immarg)328declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.fp8.v4f32.i32(i32, i32, <4 x float>)329declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.bf8.v4f32.i32(i32, i32, <4 x float>)330declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.fp8.v4f32.i32(i32, i32, <4 x float>)331declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.bf8.v4f32.i32(i32, i32, <4 x float>)332declare <4 x i32> @llvm.amdgcn.wmma.i32.16x16x32.iu4.v4i32.i32(i1 immarg, i32, i1 immarg, i32, <4 x i32>, i1 immarg)333