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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 < %s | FileCheck %s --check-prefix=W643 4declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.f16.v4f32.v16f16(<16 x half>, <16 x half>, <4 x float>)5declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf16.v4f32.v16i16(<16 x i16>, <16 x i16>, <4 x float>)6declare <8 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v8f16.v16f16(<16 x half>, <16 x half>, <8 x half>, i1 immarg)7declare <8 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v8i16.v16i16(<16 x i16>, <16 x i16>, <8 x i16>, i1 immarg)8declare <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 immarg, <4 x i32>, i1 immarg, <4 x i32>, <4 x i32>, i1 immarg)9declare <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 immarg, <2 x i32>, i1 immarg, <2 x i32>, <4 x i32>, i1 immarg)10 11; The tests demonstrate that the following WMMA register constraints are satisfied.12;13; v_wmma D, A, B, C14; A and B cannot overlap with D. C cannot partially overlap with D, but it is OK for them to be the same (which is a typical case).15;16; In each test,17; - first wmma instruction: the dest register D is different than all the sources18; - second wmma instruction: the dest register D and src2 (C) are the same19 20 21; @llvm.amdgcn.wmma.f32.16x16x16.f1622 23define amdgpu_ps void @test_wmma_f32_16x16x16_f16(<16 x half> %A, <16 x half> %B, <4 x float> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {24; W64-LABEL: test_wmma_f32_16x16x16_f16:25; W64: ; %bb.0: ; %bb26; W64-NEXT: v_wmma_f32_16x16x16_f16 v[24:27], v[0:7], v[8:15], v[16:19]27; W64-NEXT: v_wmma_f32_16x16x16_f16 v[16:19], v[8:15], v[8:15], v[16:19]28; W64-NEXT: global_store_b128 v[20:21], v[24:27], off29; W64-NEXT: global_store_b128 v[22:23], v[16:19], off30; W64-NEXT: s_endpgm31bb:32 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.f16.v4f32.v16f16(<16 x half> %A, <16 x half> %B, <4 x float> %C)33 %res2 = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.f16.v4f32.v16f16(<16 x half> %B, <16 x half> %B, <4 x float> %C)34 store <4 x float> %res, ptr addrspace(1) %out, align 1635 store <4 x float> %res2, ptr addrspace(1) %out2, align 1636 ret void37}38 39; @llvm.amdgcn.wmma.f32.16x16x16.bf1640 41define amdgpu_ps void @test_wmma_f32_16x16x16_bf16(<16 x i16> %A, <16 x i16> %B, <4 x float> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {42; W64-LABEL: test_wmma_f32_16x16x16_bf16:43; W64: ; %bb.0: ; %bb44; W64-NEXT: v_wmma_f32_16x16x16_bf16 v[24:27], v[0:7], v[8:15], v[16:19]45; W64-NEXT: v_wmma_f32_16x16x16_bf16 v[16:19], v[8:15], v[8:15], v[16:19]46; W64-NEXT: global_store_b128 v[20:21], v[24:27], off47; W64-NEXT: global_store_b128 v[22:23], v[16:19], off48; W64-NEXT: s_endpgm49bb:50 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf16.v4f32.v16i16(<16 x i16> %A, <16 x i16> %B, <4 x float> %C)51 %res2 = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf16.v4f32.v16i16(<16 x i16> %B, <16 x i16> %B, <4 x float> %C)52 store <4 x float> %res, ptr addrspace(1) %out, align 1653 store <4 x float> %res2, ptr addrspace(1) %out2, align 1654 ret void55}56 57; @llvm.amdgcn.wmma.f16.16x16x16.f1658 59define amdgpu_ps void @test_wmma_f16_16x16x16_f16_lo(<16 x half> %A, <16 x half> %B, <8 x half> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {60; W64-LABEL: test_wmma_f16_16x16x16_f16_lo:61; W64: ; %bb.0: ; %bb62; W64-NEXT: v_wmma_f16_16x16x16_f16 v[24:27], v[0:7], v[8:15], v[16:19]63; W64-NEXT: v_wmma_f16_16x16x16_f16 v[16:19], v[8:15], v[8:15], v[16:19]64; W64-NEXT: global_store_b128 v[20:21], v[24:27], off65; W64-NEXT: global_store_b128 v[22:23], v[16:19], off66; W64-NEXT: s_endpgm67bb:68 %res = call <8 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v8f16.v16f16(<16 x half> %A, <16 x half> %B, <8 x half> %C, i1 0)69 %res2 = call <8 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v8f16.v16f16(<16 x half> %B, <16 x half> %B, <8 x half> %C, i1 0)70 store <8 x half> %res, ptr addrspace(1) %out, align 1671 store <8 x half> %res2, ptr addrspace(1) %out2, align 1672 ret void73}74 75define amdgpu_ps void @test_wmma_f16_16x16x16_f16_hi(<16 x half> %A, <16 x half> %B, <8 x half> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {76; W64-LABEL: test_wmma_f16_16x16x16_f16_hi:77; W64: ; %bb.0: ; %bb78; W64-NEXT: v_wmma_f16_16x16x16_f16 v[24:27], v[0:7], v[8:15], v[16:19] op_sel:[0,0,1]79; W64-NEXT: v_wmma_f16_16x16x16_f16 v[16:19], v[8:15], v[8:15], v[16:19] op_sel:[0,0,1]80; W64-NEXT: global_store_b128 v[20:21], v[24:27], off81; W64-NEXT: global_store_b128 v[22:23], v[16:19], off82; W64-NEXT: s_endpgm83bb:84 %res = call <8 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v8f16.v16f16(<16 x half> %A, <16 x half> %B, <8 x half> %C, i1 1)85 %res2 = call <8 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v8f16.v16f16(<16 x half> %B, <16 x half> %B, <8 x half> %C, i1 1)86 store <8 x half> %res, ptr addrspace(1) %out, align 1687 store <8 x half> %res2, ptr addrspace(1) %out2, align 1688 ret void89}90 91; @llvm.amdgcn.wmma.bf16.16x16x16.bf1692 93define amdgpu_ps void @test_wmma_bf16_16x16x16_bf16_lo(<16 x i16> %A, <16 x i16> %B, <8 x i16> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {94; W64-LABEL: test_wmma_bf16_16x16x16_bf16_lo:95; W64: ; %bb.0: ; %bb96; W64-NEXT: v_wmma_bf16_16x16x16_bf16 v[24:27], v[0:7], v[8:15], v[16:19]97; W64-NEXT: v_wmma_bf16_16x16x16_bf16 v[16:19], v[8:15], v[8:15], v[16:19]98; W64-NEXT: global_store_b128 v[20:21], v[24:27], off99; W64-NEXT: global_store_b128 v[22:23], v[16:19], off100; W64-NEXT: s_endpgm101bb:102 %res = call <8 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v8i16.v16i16(<16 x i16> %A, <16 x i16> %B, <8 x i16> %C, i1 0)103 %res2 = call <8 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v8i16.v16i16(<16 x i16> %B, <16 x i16> %B, <8 x i16> %C, i1 0)104 store <8 x i16> %res, ptr addrspace(1) %out, align 16105 store <8 x i16> %res2, ptr addrspace(1) %out2, align 16106 ret void107}108 109define amdgpu_ps void @test_wmma_bf16_16x16x16_bf16_hi(<16 x i16> %A, <16 x i16> %B, <8 x i16> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {110; W64-LABEL: test_wmma_bf16_16x16x16_bf16_hi:111; W64: ; %bb.0: ; %bb112; W64-NEXT: v_wmma_bf16_16x16x16_bf16 v[24:27], v[0:7], v[8:15], v[16:19] op_sel:[0,0,1]113; W64-NEXT: v_wmma_bf16_16x16x16_bf16 v[16:19], v[8:15], v[8:15], v[16:19] op_sel:[0,0,1]114; W64-NEXT: global_store_b128 v[20:21], v[24:27], off115; W64-NEXT: global_store_b128 v[22:23], v[16:19], off116; W64-NEXT: s_endpgm117bb:118 %res = call <8 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v8i16.v16i16(<16 x i16> %A, <16 x i16> %B, <8 x i16> %C, i1 1)119 %res2 = call <8 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v8i16.v16i16(<16 x i16> %B, <16 x i16> %B, <8 x i16> %C, i1 1)120 store <8 x i16> %res, ptr addrspace(1) %out, align 16121 store <8 x i16> %res2, ptr addrspace(1) %out2, align 16122 ret void123}124 125; @llvm.amdgcn.wmma.i32.16x16x16.iu8126 127define amdgpu_ps void @test_wmma_i32_16x16x16_ui8_unsigned_unsigned(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {128; W64-LABEL: test_wmma_i32_16x16x16_ui8_unsigned_unsigned:129; W64: ; %bb.0: ; %bb130; W64-NEXT: v_wmma_i32_16x16x16_iu8 v[16:19], v[0:3], v[4:7], v[8:11]131; W64-NEXT: v_wmma_i32_16x16x16_iu8 v[8:11], v[4:7], v[4:7], v[8:11]132; W64-NEXT: global_store_b128 v[12:13], v[16:19], off133; W64-NEXT: global_store_b128 v[14:15], v[8:11], off134; W64-NEXT: s_endpgm135bb:136 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 0, <4 x i32> %A, i1 0, <4 x i32> %B, <4 x i32> %C, i1 0)137 %res2 = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 0, <4 x i32> %B, i1 0, <4 x i32> %B, <4 x i32> %C, i1 0)138 store <4 x i32> %res, ptr addrspace(1) %out, align 16139 store <4 x i32> %res2, ptr addrspace(1) %out2, align 16140 ret void141}142 143 144define amdgpu_ps void @test_wmma_i32_16x16x16_ui8_unsigned_signed(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {145; W64-LABEL: test_wmma_i32_16x16x16_ui8_unsigned_signed:146; W64: ; %bb.0: ; %bb147; W64-NEXT: v_wmma_i32_16x16x16_iu8 v[16:19], v[0:3], v[4:7], v[8:11] neg_lo:[0,1,0]148; W64-NEXT: v_wmma_i32_16x16x16_iu8 v[8:11], v[4:7], v[4:7], v[8:11] neg_lo:[0,1,0]149; W64-NEXT: global_store_b128 v[12:13], v[16:19], off150; W64-NEXT: global_store_b128 v[14:15], v[8:11], off151; W64-NEXT: s_endpgm152bb:153 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 0, <4 x i32> %A, i1 1, <4 x i32> %B, <4 x i32> %C, i1 0)154 %res2 = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 0, <4 x i32> %B, i1 1, <4 x i32> %B, <4 x i32> %C, i1 0)155 store <4 x i32> %res, ptr addrspace(1) %out, align 16156 store <4 x i32> %res2, ptr addrspace(1) %out2, align 16157 ret void158}159 160define amdgpu_ps void @test_wmma_i32_16x16x16_ui8_signed_unsigned(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {161; W64-LABEL: test_wmma_i32_16x16x16_ui8_signed_unsigned:162; W64: ; %bb.0: ; %bb163; W64-NEXT: v_wmma_i32_16x16x16_iu8 v[16:19], v[0:3], v[4:7], v[8:11] neg_lo:[1,0,0]164; W64-NEXT: v_wmma_i32_16x16x16_iu8 v[8:11], v[4:7], v[4:7], v[8:11] neg_lo:[1,0,0]165; W64-NEXT: global_store_b128 v[12:13], v[16:19], off166; W64-NEXT: global_store_b128 v[14:15], v[8:11], off167; W64-NEXT: s_endpgm168bb:169 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 1, <4 x i32> %A, i1 0, <4 x i32> %B, <4 x i32> %C, i1 0)170 %res2 = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 1, <4 x i32> %B, i1 0, <4 x i32> %B, <4 x i32> %C, i1 0)171 store <4 x i32> %res, ptr addrspace(1) %out, align 16172 store <4 x i32> %res2, ptr addrspace(1) %out2, align 16173 ret void174}175 176define amdgpu_ps void @test_wmma_i32_16x16x16_ui8_signed_signed(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {177; W64-LABEL: test_wmma_i32_16x16x16_ui8_signed_signed:178; W64: ; %bb.0: ; %bb179; W64-NEXT: v_wmma_i32_16x16x16_iu8 v[16:19], v[0:3], v[4:7], v[8:11] neg_lo:[1,1,0]180; W64-NEXT: v_wmma_i32_16x16x16_iu8 v[8:11], v[4:7], v[4:7], v[8:11] neg_lo:[1,1,0]181; W64-NEXT: global_store_b128 v[12:13], v[16:19], off182; W64-NEXT: global_store_b128 v[14:15], v[8:11], off183; W64-NEXT: s_endpgm184bb:185 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 1, <4 x i32> %A, i1 1, <4 x i32> %B, <4 x i32> %C, i1 0)186 %res2 = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 1, <4 x i32> %B, i1 1, <4 x i32> %B, <4 x i32> %C, i1 0)187 store <4 x i32> %res, ptr addrspace(1) %out, align 16188 store <4 x i32> %res2, ptr addrspace(1) %out2, align 16189 ret void190}191 192define amdgpu_ps void @test_wmma_i32_16x16x16_ui8_unsigned_unsigned_clamp(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {193; W64-LABEL: test_wmma_i32_16x16x16_ui8_unsigned_unsigned_clamp:194; W64: ; %bb.0: ; %bb195; W64-NEXT: v_wmma_i32_16x16x16_iu8 v[16:19], v[0:3], v[4:7], v[8:11] clamp196; W64-NEXT: v_wmma_i32_16x16x16_iu8 v[8:11], v[4:7], v[4:7], v[8:11] clamp197; W64-NEXT: global_store_b128 v[12:13], v[16:19], off198; W64-NEXT: global_store_b128 v[14:15], v[8:11], off199; W64-NEXT: s_endpgm200bb:201 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 0, <4 x i32> %A, i1 0, <4 x i32> %B, <4 x i32> %C, i1 1)202 %res2 = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 0, <4 x i32> %B, i1 0, <4 x i32> %B, <4 x i32> %C, i1 1)203 store <4 x i32> %res, ptr addrspace(1) %out, align 16204 store <4 x i32> %res2, ptr addrspace(1) %out2, align 16205 ret void206}207 208define amdgpu_ps void @test_wmma_i32_16x16x16_ui8_unsigned_signed_clamp(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {209; W64-LABEL: test_wmma_i32_16x16x16_ui8_unsigned_signed_clamp:210; W64: ; %bb.0: ; %bb211; W64-NEXT: v_wmma_i32_16x16x16_iu8 v[16:19], v[0:3], v[4:7], v[8:11] neg_lo:[0,1,0] clamp212; W64-NEXT: v_wmma_i32_16x16x16_iu8 v[8:11], v[4:7], v[4:7], v[8:11] neg_lo:[0,1,0] clamp213; W64-NEXT: global_store_b128 v[12:13], v[16:19], off214; W64-NEXT: global_store_b128 v[14:15], v[8:11], off215; W64-NEXT: s_endpgm216bb:217 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 0, <4 x i32> %A, i1 1, <4 x i32> %B, <4 x i32> %C, i1 1)218 %res2 = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 0, <4 x i32> %B, i1 1, <4 x i32> %B, <4 x i32> %C, i1 1)219 store <4 x i32> %res, ptr addrspace(1) %out, align 16220 store <4 x i32> %res2, ptr addrspace(1) %out2, align 16221 ret void222}223 224define amdgpu_ps void @test_wmma_i32_16x16x16_ui8_signed_unsigned_clamp(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {225; W64-LABEL: test_wmma_i32_16x16x16_ui8_signed_unsigned_clamp:226; W64: ; %bb.0: ; %bb227; W64-NEXT: v_wmma_i32_16x16x16_iu8 v[16:19], v[0:3], v[4:7], v[8:11] neg_lo:[1,0,0] clamp228; W64-NEXT: v_wmma_i32_16x16x16_iu8 v[8:11], v[4:7], v[4:7], v[8:11] neg_lo:[1,0,0] clamp229; W64-NEXT: global_store_b128 v[12:13], v[16:19], off230; W64-NEXT: global_store_b128 v[14:15], v[8:11], off231; W64-NEXT: s_endpgm232bb:233 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 1, <4 x i32> %A, i1 0, <4 x i32> %B, <4 x i32> %C, i1 1)234 %res2 = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 1, <4 x i32> %B, i1 0, <4 x i32> %B, <4 x i32> %C, i1 1)235 store <4 x i32> %res, ptr addrspace(1) %out, align 16236 store <4 x i32> %res2, ptr addrspace(1) %out2, align 16237 ret void238}239 240define amdgpu_ps void @test_wmma_i32_16x16x16_ui8_signed_signed_clamp(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {241; W64-LABEL: test_wmma_i32_16x16x16_ui8_signed_signed_clamp:242; W64: ; %bb.0: ; %bb243; W64-NEXT: v_wmma_i32_16x16x16_iu8 v[16:19], v[0:3], v[4:7], v[8:11] neg_lo:[1,1,0] clamp244; W64-NEXT: v_wmma_i32_16x16x16_iu8 v[8:11], v[4:7], v[4:7], v[8:11] neg_lo:[1,1,0] clamp245; W64-NEXT: global_store_b128 v[12:13], v[16:19], off246; W64-NEXT: global_store_b128 v[14:15], v[8:11], off247; W64-NEXT: s_endpgm248bb:249 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 1, <4 x i32> %A, i1 1, <4 x i32> %B, <4 x i32> %C, i1 1)250 %res2 = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.v4i32(i1 1, <4 x i32> %B, i1 1, <4 x i32> %B, <4 x i32> %C, i1 1)251 store <4 x i32> %res, ptr addrspace(1) %out, align 16252 store <4 x i32> %res2, ptr addrspace(1) %out2, align 16253 ret void254}255 256; @llvm.amdgcn.wmma.i32.16x16x16.iu4257 258define amdgpu_ps void @test_wmma_i32_16x16x16_ui4_unsigned_unsigned(<2 x i32> %A, <2 x i32> %B, <4 x i32> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {259; W64-LABEL: test_wmma_i32_16x16x16_ui4_unsigned_unsigned:260; W64: ; %bb.0: ; %bb261; W64-NEXT: v_wmma_i32_16x16x16_iu4 v[12:15], v[0:1], v[2:3], v[4:7]262; W64-NEXT: v_wmma_i32_16x16x16_iu4 v[4:7], v[2:3], v[2:3], v[4:7]263; W64-NEXT: global_store_b128 v[8:9], v[12:15], off264; W64-NEXT: global_store_b128 v[10:11], v[4:7], off265; W64-NEXT: s_endpgm266bb:267 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 0, <2 x i32> %A, i1 0, <2 x i32> %B, <4 x i32> %C, i1 0)268 %res2 = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 0, <2 x i32> %B, i1 0, <2 x i32> %B, <4 x i32> %C, i1 0)269 store <4 x i32> %res, ptr addrspace(1) %out, align 16270 store <4 x i32> %res2, ptr addrspace(1) %out2, align 16271 ret void272}273 274define amdgpu_ps void @test_wmma_i32_16x16x16_ui4_unsigned_signed(<2 x i32> %A, <2 x i32> %B, <4 x i32> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {275; W64-LABEL: test_wmma_i32_16x16x16_ui4_unsigned_signed:276; W64: ; %bb.0: ; %bb277; W64-NEXT: v_wmma_i32_16x16x16_iu4 v[12:15], v[0:1], v[2:3], v[4:7] neg_lo:[0,1,0]278; W64-NEXT: v_wmma_i32_16x16x16_iu4 v[4:7], v[2:3], v[2:3], v[4:7] neg_lo:[0,1,0]279; W64-NEXT: global_store_b128 v[8:9], v[12:15], off280; W64-NEXT: global_store_b128 v[10:11], v[4:7], off281; W64-NEXT: s_endpgm282bb:283 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 0, <2 x i32> %A, i1 1, <2 x i32> %B, <4 x i32> %C, i1 0)284 %res2 = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 0, <2 x i32> %B, i1 1, <2 x i32> %B, <4 x i32> %C, i1 0)285 store <4 x i32> %res, ptr addrspace(1) %out, align 16286 store <4 x i32> %res2, ptr addrspace(1) %out2, align 16287 ret void288}289 290define amdgpu_ps void @test_wmma_i32_16x16x16_ui4_signed_unsigned(<2 x i32> %A, <2 x i32> %B, <4 x i32> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {291; W64-LABEL: test_wmma_i32_16x16x16_ui4_signed_unsigned:292; W64: ; %bb.0: ; %bb293; W64-NEXT: v_wmma_i32_16x16x16_iu4 v[12:15], v[0:1], v[2:3], v[4:7] neg_lo:[1,0,0]294; W64-NEXT: v_wmma_i32_16x16x16_iu4 v[4:7], v[2:3], v[2:3], v[4:7] neg_lo:[1,0,0]295; W64-NEXT: global_store_b128 v[8:9], v[12:15], off296; W64-NEXT: global_store_b128 v[10:11], v[4:7], off297; W64-NEXT: s_endpgm298bb:299 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 1, <2 x i32> %A, i1 0, <2 x i32> %B, <4 x i32> %C, i1 0)300 %res2 = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 1, <2 x i32> %B, i1 0, <2 x i32> %B, <4 x i32> %C, i1 0)301 store <4 x i32> %res, ptr addrspace(1) %out, align 16302 store <4 x i32> %res2, ptr addrspace(1) %out2, align 16303 ret void304}305 306define amdgpu_ps void @test_wmma_i32_16x16x16_ui4_signed_signed(<2 x i32> %A, <2 x i32> %B, <4 x i32> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {307; W64-LABEL: test_wmma_i32_16x16x16_ui4_signed_signed:308; W64: ; %bb.0: ; %bb309; W64-NEXT: v_wmma_i32_16x16x16_iu4 v[12:15], v[0:1], v[2:3], v[4:7] neg_lo:[1,1,0]310; W64-NEXT: v_wmma_i32_16x16x16_iu4 v[4:7], v[2:3], v[2:3], v[4:7] neg_lo:[1,1,0]311; W64-NEXT: global_store_b128 v[8:9], v[12:15], off312; W64-NEXT: global_store_b128 v[10:11], v[4:7], off313; W64-NEXT: s_endpgm314bb:315 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 1, <2 x i32> %A, i1 1, <2 x i32> %B, <4 x i32> %C, i1 0)316 %res2 = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 1, <2 x i32> %B, i1 1, <2 x i32> %B, <4 x i32> %C, i1 0)317 store <4 x i32> %res, ptr addrspace(1) %out, align 16318 store <4 x i32> %res2, ptr addrspace(1) %out2, align 16319 ret void320}321 322define amdgpu_ps void @test_wmma_i32_16x16x16_ui4_unsigned_unsigned_clamp(<2 x i32> %A, <2 x i32> %B, <4 x i32> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {323; W64-LABEL: test_wmma_i32_16x16x16_ui4_unsigned_unsigned_clamp:324; W64: ; %bb.0: ; %bb325; W64-NEXT: v_wmma_i32_16x16x16_iu4 v[12:15], v[0:1], v[2:3], v[4:7] clamp326; W64-NEXT: v_wmma_i32_16x16x16_iu4 v[4:7], v[2:3], v[2:3], v[4:7] clamp327; W64-NEXT: global_store_b128 v[8:9], v[12:15], off328; W64-NEXT: global_store_b128 v[10:11], v[4:7], off329; W64-NEXT: s_endpgm330bb:331 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 0, <2 x i32> %A, i1 0, <2 x i32> %B, <4 x i32> %C, i1 1)332 %res2 = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 0, <2 x i32> %B, i1 0, <2 x i32> %B, <4 x i32> %C, i1 1)333 store <4 x i32> %res, ptr addrspace(1) %out, align 16334 store <4 x i32> %res2, ptr addrspace(1) %out2, align 16335 ret void336}337 338define amdgpu_ps void @test_wmma_i32_16x16x16_ui4_unsigned_signed_clamp(<2 x i32> %A, <2 x i32> %B, <4 x i32> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {339; W64-LABEL: test_wmma_i32_16x16x16_ui4_unsigned_signed_clamp:340; W64: ; %bb.0: ; %bb341; W64-NEXT: v_wmma_i32_16x16x16_iu4 v[12:15], v[0:1], v[2:3], v[4:7] neg_lo:[0,1,0] clamp342; W64-NEXT: v_wmma_i32_16x16x16_iu4 v[4:7], v[2:3], v[2:3], v[4:7] neg_lo:[0,1,0] clamp343; W64-NEXT: global_store_b128 v[8:9], v[12:15], off344; W64-NEXT: global_store_b128 v[10:11], v[4:7], off345; W64-NEXT: s_endpgm346bb:347 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 0, <2 x i32> %A, i1 1, <2 x i32> %B, <4 x i32> %C, i1 1)348 %res2 = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 0, <2 x i32> %B, i1 1, <2 x i32> %B, <4 x i32> %C, i1 1)349 store <4 x i32> %res, ptr addrspace(1) %out, align 16350 store <4 x i32> %res2, ptr addrspace(1) %out2, align 16351 ret void352}353 354define amdgpu_ps void @test_wmma_i32_16x16x16_ui4_signed_unsigned_clamp(<2 x i32> %A, <2 x i32> %B, <4 x i32> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {355; W64-LABEL: test_wmma_i32_16x16x16_ui4_signed_unsigned_clamp:356; W64: ; %bb.0: ; %bb357; W64-NEXT: v_wmma_i32_16x16x16_iu4 v[12:15], v[0:1], v[2:3], v[4:7] neg_lo:[1,0,0] clamp358; W64-NEXT: v_wmma_i32_16x16x16_iu4 v[4:7], v[2:3], v[2:3], v[4:7] neg_lo:[1,0,0] clamp359; W64-NEXT: global_store_b128 v[8:9], v[12:15], off360; W64-NEXT: global_store_b128 v[10:11], v[4:7], off361; W64-NEXT: s_endpgm362bb:363 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 1, <2 x i32> %A, i1 0, <2 x i32> %B, <4 x i32> %C, i1 1)364 %res2 = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 1, <2 x i32> %B, i1 0, <2 x i32> %B, <4 x i32> %C, i1 1)365 store <4 x i32> %res, ptr addrspace(1) %out, align 16366 store <4 x i32> %res2, ptr addrspace(1) %out2, align 16367 ret void368}369 370define amdgpu_ps void @test_wmma_i32_16x16x16_ui4_signed_signed_clamp(<2 x i32> %A, <2 x i32> %B, <4 x i32> %C, ptr addrspace(1) %out, ptr addrspace(1) %out2) {371; W64-LABEL: test_wmma_i32_16x16x16_ui4_signed_signed_clamp:372; W64: ; %bb.0: ; %bb373; W64-NEXT: v_wmma_i32_16x16x16_iu4 v[12:15], v[0:1], v[2:3], v[4:7] neg_lo:[1,1,0] clamp374; W64-NEXT: v_wmma_i32_16x16x16_iu4 v[4:7], v[2:3], v[2:3], v[4:7] neg_lo:[1,1,0] clamp375; W64-NEXT: global_store_b128 v[8:9], v[12:15], off376; W64-NEXT: global_store_b128 v[10:11], v[4:7], off377; W64-NEXT: s_endpgm378bb:379 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 1, <2 x i32> %A, i1 1, <2 x i32> %B, <4 x i32> %C, i1 1)380 %res2 = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.v2i32(i1 1, <2 x i32> %B, i1 1, <2 x i32> %B, <4 x i32> %C, i1 1)381 store <4 x i32> %res, ptr addrspace(1) %out, align 16382 store <4 x i32> %res2, ptr addrspace(1) %out2, align 16383 ret void384}385 386