328 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1200 %s5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1200 %s6; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s7; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -global-isel=1 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s8 9define amdgpu_kernel void @workgroup_id_x(ptr addrspace(1) %ptrx) {10;11; GFX9-LABEL: workgroup_id_x:12; GFX9: ; %bb.0:13; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x014; GFX9-NEXT: v_mov_b32_e32 v0, ttmp915; GFX9-NEXT: v_mov_b32_e32 v1, 016; GFX9-NEXT: s_waitcnt lgkmcnt(0)17; GFX9-NEXT: global_store_dword v1, v0, s[0:1]18; GFX9-NEXT: s_endpgm19;20; GFX1200-LABEL: workgroup_id_x:21; GFX1200: ; %bb.0:22; GFX1200-NEXT: s_load_b64 s[0:1], s[4:5], 0x023; GFX1200-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 024; GFX1200-NEXT: s_wait_kmcnt 0x025; GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]26; GFX1200-NEXT: s_endpgm27;28; GFX1250-SDAG-LABEL: workgroup_id_x:29; GFX1250-SDAG: ; %bb.0:30; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 131; GFX1250-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x032; GFX1250-SDAG-NEXT: s_bfe_u32 s2, ttmp6, 0x4000c33; GFX1250-SDAG-NEXT: s_and_b32 s3, ttmp6, 1534; GFX1250-SDAG-NEXT: s_add_co_i32 s2, s2, 135; GFX1250-SDAG-NEXT: s_wait_xcnt 0x036; GFX1250-SDAG-NEXT: s_getreg_b32 s4, hwreg(HW_REG_IB_STS2, 6, 4)37; GFX1250-SDAG-NEXT: s_mul_i32 s2, ttmp9, s238; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)39; GFX1250-SDAG-NEXT: s_add_co_i32 s3, s3, s240; GFX1250-SDAG-NEXT: s_cmp_eq_u32 s4, 041; GFX1250-SDAG-NEXT: s_cselect_b32 s2, ttmp9, s342; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s243; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x044; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]45; GFX1250-SDAG-NEXT: s_endpgm46;47; GFX1250-GISEL-LABEL: workgroup_id_x:48; GFX1250-GISEL: ; %bb.0:49; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 150; GFX1250-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x051; GFX1250-GISEL-NEXT: s_bfe_u32 s2, ttmp6, 0x4000c52; GFX1250-GISEL-NEXT: s_and_b32 s3, ttmp6, 1553; GFX1250-GISEL-NEXT: s_add_co_i32 s2, s2, 154; GFX1250-GISEL-NEXT: s_wait_xcnt 0x055; GFX1250-GISEL-NEXT: s_getreg_b32 s4, hwreg(HW_REG_IB_STS2, 6, 4)56; GFX1250-GISEL-NEXT: s_mul_i32 s2, ttmp9, s257; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 058; GFX1250-GISEL-NEXT: s_add_co_i32 s3, s3, s259; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s4, 060; GFX1250-GISEL-NEXT: s_cselect_b32 s2, ttmp9, s361; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)62; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, s263; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x064; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]65; GFX1250-GISEL-NEXT: s_endpgm66; GFX12-LABEL: workgroup_id_x:67; GFX12: ; %bb.0:68; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x069; GFX12-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 070; GFX12-NEXT: s_wait_kmcnt 0x071; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]72; GFX12-NEXT: s_endpgm73 %idx = call i32 @llvm.amdgcn.workgroup.id.x()74 store i32 %idx, ptr addrspace(1) %ptrx75 76 ret void77}78 79define amdgpu_kernel void @workgroup_id_xy(ptr addrspace(1) %ptrx, ptr addrspace(1) %ptry) {80; GFX9-LABEL: workgroup_id_xy:81; GFX9: ; %bb.0:82; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x083; GFX9-NEXT: v_mov_b32_e32 v0, ttmp984; GFX9-NEXT: v_mov_b32_e32 v1, 085; GFX9-NEXT: s_and_b32 s4, ttmp7, 0xffff86; GFX9-NEXT: v_mov_b32_e32 v2, s487; GFX9-NEXT: s_waitcnt lgkmcnt(0)88; GFX9-NEXT: global_store_dword v1, v0, s[0:1]89; GFX9-NEXT: global_store_dword v1, v2, s[2:3]90; GFX9-NEXT: s_endpgm91;92; GFX1200-LABEL: workgroup_id_xy:93; GFX1200: ; %bb.0:94; GFX1200-NEXT: s_load_b128 s[0:3], s[4:5], 0x095; GFX1200-NEXT: s_and_b32 s4, ttmp7, 0xffff96; GFX1200-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 097; GFX1200-NEXT: v_mov_b32_e32 v2, s498; GFX1200-NEXT: s_wait_kmcnt 0x099; GFX1200-NEXT: s_clause 0x1100; GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]101; GFX1200-NEXT: global_store_b32 v1, v2, s[2:3]102; GFX1200-NEXT: s_endpgm103;104; GFX1250-SDAG-LABEL: workgroup_id_xy:105; GFX1250-SDAG: ; %bb.0:106; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1107; GFX1250-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x0108; GFX1250-SDAG-NEXT: s_bfe_u32 s6, ttmp6, 0x40010109; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0110; GFX1250-SDAG-NEXT: s_and_b32 s4, ttmp7, 0xffff111; GFX1250-SDAG-NEXT: s_add_co_i32 s6, s6, 1112; GFX1250-SDAG-NEXT: s_bfe_u32 s7, ttmp6, 0x4000c113; GFX1250-SDAG-NEXT: s_mul_i32 s5, s4, s6114; GFX1250-SDAG-NEXT: s_bfe_u32 s6, ttmp6, 0x40004115; GFX1250-SDAG-NEXT: s_add_co_i32 s7, s7, 1116; GFX1250-SDAG-NEXT: s_add_co_i32 s6, s6, s5117; GFX1250-SDAG-NEXT: s_and_b32 s5, ttmp6, 15118; GFX1250-SDAG-NEXT: s_mul_i32 s7, ttmp9, s7119; GFX1250-SDAG-NEXT: s_getreg_b32 s8, hwreg(HW_REG_IB_STS2, 6, 4)120; GFX1250-SDAG-NEXT: s_add_co_i32 s5, s5, s7121; GFX1250-SDAG-NEXT: s_cmp_eq_u32 s8, 0122; GFX1250-SDAG-NEXT: s_cselect_b32 s5, ttmp9, s5123; GFX1250-SDAG-NEXT: s_cselect_b32 s4, s4, s6124; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5125; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, s4126; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0127; GFX1250-SDAG-NEXT: s_clause 0x1128; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]129; GFX1250-SDAG-NEXT: global_store_b32 v0, v2, s[2:3]130; GFX1250-SDAG-NEXT: s_endpgm131;132; GFX1250-GISEL-LABEL: workgroup_id_xy:133; GFX1250-GISEL: ; %bb.0:134; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1135; GFX1250-GISEL-NEXT: s_bfe_u32 s6, ttmp6, 0x4000c136; GFX1250-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x0137; GFX1250-GISEL-NEXT: s_add_co_i32 s6, s6, 1138; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0139; GFX1250-GISEL-NEXT: s_and_b32 s4, ttmp6, 15140; GFX1250-GISEL-NEXT: s_mul_i32 s5, ttmp9, s6141; GFX1250-GISEL-NEXT: s_getreg_b32 s6, hwreg(HW_REG_IB_STS2, 6, 4)142; GFX1250-GISEL-NEXT: s_add_co_i32 s4, s4, s5143; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s6, 0144; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0145; GFX1250-GISEL-NEXT: s_cselect_b32 s4, ttmp9, s4146; GFX1250-GISEL-NEXT: s_bfe_u32 s5, ttmp6, 0x40010147; GFX1250-GISEL-NEXT: s_and_b32 s7, ttmp7, 0xffff148; GFX1250-GISEL-NEXT: s_add_co_i32 s5, s5, 1149; GFX1250-GISEL-NEXT: s_bfe_u32 s8, ttmp6, 0x40004150; GFX1250-GISEL-NEXT: s_mul_i32 s5, s7, s5151; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, s4152; GFX1250-GISEL-NEXT: s_add_co_i32 s8, s8, s5153; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s6, 0154; GFX1250-GISEL-NEXT: s_cselect_b32 s4, s7, s8155; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)156; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, s4157; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0158; GFX1250-GISEL-NEXT: s_clause 0x1159; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]160; GFX1250-GISEL-NEXT: global_store_b32 v1, v2, s[2:3]161; GFX1250-GISEL-NEXT: s_endpgm162; GFX12-LABEL: workgroup_id_xy:163; GFX12: ; %bb.0:164; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x0165; GFX12-NEXT: s_and_b32 s4, ttmp7, 0xffff166; GFX12-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 0167; GFX12-NEXT: v_mov_b32_e32 v2, s4168; GFX12-NEXT: s_wait_kmcnt 0x0169; GFX12-NEXT: s_clause 0x1170; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]171; GFX12-NEXT: global_store_b32 v1, v2, s[2:3]172; GFX12-NEXT: s_endpgm173 %idx = call i32 @llvm.amdgcn.workgroup.id.x()174 store i32 %idx, ptr addrspace(1) %ptrx175 %idy = call i32 @llvm.amdgcn.workgroup.id.y()176 store i32 %idy, ptr addrspace(1) %ptry177 178 ret void179}180 181define amdgpu_kernel void @workgroup_id_xyz(ptr addrspace(1) %ptrx, ptr addrspace(1) %ptry, ptr addrspace(1) %ptrz) {182; GFX9-LABEL: workgroup_id_xyz:183; GFX9: ; %bb.0:184; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0185; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10186; GFX9-NEXT: v_mov_b32_e32 v0, ttmp9187; GFX9-NEXT: v_mov_b32_e32 v1, 0188; GFX9-NEXT: s_and_b32 s6, ttmp7, 0xffff189; GFX9-NEXT: s_waitcnt lgkmcnt(0)190; GFX9-NEXT: global_store_dword v1, v0, s[0:1]191; GFX9-NEXT: v_mov_b32_e32 v0, s6192; GFX9-NEXT: s_lshr_b32 s0, ttmp7, 16193; GFX9-NEXT: global_store_dword v1, v0, s[2:3]194; GFX9-NEXT: v_mov_b32_e32 v0, s0195; GFX9-NEXT: global_store_dword v1, v0, s[4:5]196; GFX9-NEXT: s_endpgm197;198; GFX1200-LABEL: workgroup_id_xyz:199; GFX1200: ; %bb.0:200; GFX1200-NEXT: s_clause 0x1201; GFX1200-NEXT: s_load_b128 s[0:3], s[4:5], 0x0202; GFX1200-NEXT: s_load_b64 s[4:5], s[4:5], 0x10203; GFX1200-NEXT: s_and_b32 s6, ttmp7, 0xffff204; GFX1200-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 0205; GFX1200-NEXT: s_lshr_b32 s7, ttmp7, 16206; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)207; GFX1200-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7208; GFX1200-NEXT: s_wait_kmcnt 0x0209; GFX1200-NEXT: s_clause 0x2210; GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]211; GFX1200-NEXT: global_store_b32 v1, v2, s[2:3]212; GFX1200-NEXT: global_store_b32 v1, v3, s[4:5]213; GFX1200-NEXT: s_endpgm214;215; GFX1250-SDAG-LABEL: workgroup_id_xyz:216; GFX1250-SDAG: ; %bb.0:217; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1218; GFX1250-SDAG-NEXT: s_bfe_u32 s0, ttmp6, 0x40014219; GFX1250-SDAG-NEXT: s_lshr_b32 s8, ttmp7, 16220; GFX1250-SDAG-NEXT: s_add_co_i32 s9, s0, 1221; GFX1250-SDAG-NEXT: s_clause 0x1222; GFX1250-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x0223; GFX1250-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x10224; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0225; GFX1250-SDAG-NEXT: s_mul_i32 s4, s8, s9226; GFX1250-SDAG-NEXT: s_bfe_u32 s9, ttmp6, 0x40010227; GFX1250-SDAG-NEXT: s_bfe_u32 s5, ttmp6, 0x40008228; GFX1250-SDAG-NEXT: s_and_b32 s10, ttmp7, 0xffff229; GFX1250-SDAG-NEXT: s_add_co_i32 s9, s9, 1230; GFX1250-SDAG-NEXT: s_bfe_u32 s11, ttmp6, 0x4000c231; GFX1250-SDAG-NEXT: s_add_co_i32 s5, s5, s4232; GFX1250-SDAG-NEXT: s_mul_i32 s4, s10, s9233; GFX1250-SDAG-NEXT: s_bfe_u32 s9, ttmp6, 0x40004234; GFX1250-SDAG-NEXT: s_add_co_i32 s11, s11, 1235; GFX1250-SDAG-NEXT: s_add_co_i32 s9, s9, s4236; GFX1250-SDAG-NEXT: s_and_b32 s4, ttmp6, 15237; GFX1250-SDAG-NEXT: s_mul_i32 s11, ttmp9, s11238; GFX1250-SDAG-NEXT: s_getreg_b32 s12, hwreg(HW_REG_IB_STS2, 6, 4)239; GFX1250-SDAG-NEXT: s_add_co_i32 s4, s4, s11240; GFX1250-SDAG-NEXT: s_cmp_eq_u32 s12, 0241; GFX1250-SDAG-NEXT: s_cselect_b32 s4, ttmp9, s4242; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)243; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4244; GFX1250-SDAG-NEXT: s_cselect_b32 s4, s10, s9245; GFX1250-SDAG-NEXT: s_cselect_b32 s5, s8, s5246; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5247; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0248; GFX1250-SDAG-NEXT: s_clause 0x2249; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]250; GFX1250-SDAG-NEXT: global_store_b32 v0, v2, s[2:3]251; GFX1250-SDAG-NEXT: global_store_b32 v0, v3, s[6:7]252; GFX1250-SDAG-NEXT: s_endpgm253;254; GFX1250-GISEL-LABEL: workgroup_id_xyz:255; GFX1250-GISEL: ; %bb.0:256; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1257; GFX1250-GISEL-NEXT: s_bfe_u32 s0, ttmp6, 0x4000c258; GFX1250-GISEL-NEXT: s_and_b32 s1, ttmp6, 15259; GFX1250-GISEL-NEXT: s_add_co_i32 s0, s0, 1260; GFX1250-GISEL-NEXT: s_getreg_b32 s8, hwreg(HW_REG_IB_STS2, 6, 4)261; GFX1250-GISEL-NEXT: s_mul_i32 s0, ttmp9, s0262; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0263; GFX1250-GISEL-NEXT: s_add_co_i32 s1, s1, s0264; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s8, 0265; GFX1250-GISEL-NEXT: s_cselect_b32 s9, ttmp9, s1266; GFX1250-GISEL-NEXT: s_bfe_u32 s0, ttmp6, 0x40010267; GFX1250-GISEL-NEXT: s_and_b32 s10, ttmp7, 0xffff268; GFX1250-GISEL-NEXT: s_add_co_i32 s0, s0, 1269; GFX1250-GISEL-NEXT: s_bfe_u32 s11, ttmp6, 0x40004270; GFX1250-GISEL-NEXT: s_mul_i32 s12, s10, s0271; GFX1250-GISEL-NEXT: s_clause 0x1272; GFX1250-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x0273; GFX1250-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x10274; GFX1250-GISEL-NEXT: s_add_co_i32 s11, s11, s12275; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s8, 0276; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, s9277; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0278; GFX1250-GISEL-NEXT: s_cselect_b32 s4, s10, s11279; GFX1250-GISEL-NEXT: s_bfe_u32 s5, ttmp6, 0x40014280; GFX1250-GISEL-NEXT: s_lshr_b32 s10, ttmp7, 16281; GFX1250-GISEL-NEXT: s_add_co_i32 s5, s5, 1282; GFX1250-GISEL-NEXT: s_bfe_u32 s11, ttmp6, 0x40008283; GFX1250-GISEL-NEXT: s_mul_i32 s5, s10, s5284; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)285; GFX1250-GISEL-NEXT: s_add_co_i32 s11, s11, s5286; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s8, 0287; GFX1250-GISEL-NEXT: s_cselect_b32 s5, s10, s11288; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5289; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0290; GFX1250-GISEL-NEXT: s_clause 0x2291; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]292; GFX1250-GISEL-NEXT: global_store_b32 v1, v2, s[2:3]293; GFX1250-GISEL-NEXT: global_store_b32 v1, v3, s[6:7]294; GFX1250-GISEL-NEXT: s_endpgm295; GFX12-LABEL: workgroup_id_xyz:296; GFX12: ; %bb.0:297; GFX12-NEXT: s_clause 0x1298; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x0299; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x10300; GFX12-NEXT: s_and_b32 s6, ttmp7, 0xffff301; GFX12-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 0302; GFX12-NEXT: s_lshr_b32 s7, ttmp7, 16303; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)304; GFX12-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7305; GFX12-NEXT: s_wait_kmcnt 0x0306; GFX12-NEXT: s_clause 0x2307; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]308; GFX12-NEXT: global_store_b32 v1, v2, s[2:3]309; GFX12-NEXT: global_store_b32 v1, v3, s[4:5]310; GFX12-NEXT: s_endpgm311 %idx = call i32 @llvm.amdgcn.workgroup.id.x()312 store i32 %idx, ptr addrspace(1) %ptrx313 %idy = call i32 @llvm.amdgcn.workgroup.id.y()314 store i32 %idy, ptr addrspace(1) %ptry315 %idz = call i32 @llvm.amdgcn.workgroup.id.z()316 store i32 %idz, ptr addrspace(1) %ptrz317 318 ret void319}320 321declare i32 @llvm.amdgcn.workgroup.id.x()322declare i32 @llvm.amdgcn.workgroup.id.y()323declare i32 @llvm.amdgcn.workgroup.id.z()324;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:325; GFX1250: {{.*}}326; GFX9-GISEL: {{.*}}327; GFX9-SDAG: {{.*}}328