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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 22# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-wqm -o - %s | FileCheck %s3# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -passes=si-wqm -o - %s | FileCheck %s4 5--- |6 define amdgpu_ps void @exit_to_exact() {7 ret void8 }9...10---11 12---13name: exit_to_exact14tracksRegLiveness: true15registers:16 - { id: 0, class: sgpr_32, preferred-register: '' }17 - { id: 1, class: vreg_64, preferred-register: '' }18 - { id: 2, class: sgpr_256, preferred-register: '' }19 - { id: 3, class: sgpr_128, preferred-register: '' }20 - { id: 4, class: vreg_96, preferred-register: '' }21 - { id: 5, class: vreg_64, preferred-register: '' }22 - { id: 6, class: vgpr_32, preferred-register: '' }23liveins:24 - { reg: '$sgpr0', virtual-reg: '%0' }25body: |26 ; CHECK-LABEL: name: exit_to_exact27 ; CHECK: bb.0:28 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)29 ; CHECK-NEXT: liveins: $sgpr0, $vgpr0_vgpr130 ; CHECK-NEXT: {{ $}}31 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $exec_lo32 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr033 ; CHECK-NEXT: $exec_lo = S_WQM_B32 $exec_lo, implicit-def $scc34 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr135 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF36 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF37 ; CHECK-NEXT: S_CMP_EQ_U32 [[COPY1]], 0, implicit-def $scc38 ; CHECK-NEXT: undef [[V_MUL_F32_e64_:%[0-9]+]].sub0:vreg_64 = V_MUL_F32_e64 0, [[COPY2]].sub0, 0, [[COPY2]].sub1, 0, 0, implicit $mode, implicit $exec39 ; CHECK-NEXT: [[V_MUL_F32_e64_:%[0-9]+]].sub1:vreg_64 = V_MUL_F32_e64 0, [[COPY2]].sub0, 0, [[COPY2]].sub1, 0, 0, implicit $mode, implicit $exec40 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc41 ; CHECK-NEXT: $exec_lo = S_AND_B32 $exec_lo, [[COPY]], implicit-def $scc42 ; CHECK-NEXT: $scc = COPY [[COPY3]]43 ; CHECK-NEXT: [[IMAGE_SAMPLE_V3_V2_gfx10_:%[0-9]+]]:vreg_96 = IMAGE_SAMPLE_V3_V2_gfx10 [[V_MUL_F32_e64_]], [[DEF]], [[DEF1]], 7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s96), align 16, addrspace 8)44 ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc45 ; CHECK-NEXT: S_BRANCH %bb.146 ; CHECK-NEXT: {{ $}}47 ; CHECK-NEXT: bb.1:48 ; CHECK-NEXT: successors: %bb.2(0x80000000)49 ; CHECK-NEXT: {{ $}}50 ; CHECK-NEXT: bb.2:51 ; CHECK-NEXT: [[V_SUB_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_SUB_F32_e64 0, [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub0, 0, [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub1, 0, 0, implicit $mode, implicit $exec52 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET_exact [[V_SUB_F32_e64_]], [[DEF1]], [[COPY1]], 4, 0, 0, implicit $exec53 ; CHECK-NEXT: EXP 0, [[V_SUB_F32_e64_]], [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub0, [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub1, [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub2, 0, 0, 0, implicit $exec54 ; CHECK-NEXT: S_ENDPGM 055 bb.0:56 liveins: $sgpr0, $vgpr0_vgpr157 58 %0 = COPY $sgpr059 %1 = COPY $vgpr0_vgpr160 %2 = IMPLICIT_DEF61 %3 = IMPLICIT_DEF62 63 S_CMP_EQ_U32 %0, 0, implicit-def $scc64 undef %5.sub0 = V_MUL_F32_e64 0, %1.sub0, 0, %1.sub1, 0, 0, implicit $mode, implicit $exec65 %5.sub1 = V_MUL_F32_e64 0, %1.sub0, 0, %1.sub1, 0, 0, implicit $mode, implicit $exec66 %4 = IMAGE_SAMPLE_V3_V2_gfx10 %5, %2, %3, 7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s96), align 16, addrspace 8)67 S_CBRANCH_SCC1 %bb.2, implicit killed $scc68 S_BRANCH %bb.169 70 bb.1:71 72 bb.2:73 %6 = nofpexcept V_SUB_F32_e64 0, %4.sub0, 0, %4.sub1, 0, 0, implicit $mode, implicit $exec74 BUFFER_STORE_DWORD_OFFSET_exact %6, %3, %0, 4, 0, 0, implicit $exec75 EXP 0, %6, %4.sub0, %4.sub1, %4.sub2, 0, 0, 0, implicit $exec76 S_ENDPGM 077 78...79