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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass si-wqm -o - %s | FileCheck %s3# RUN: llc -mtriple=amdgcn -mcpu=fiji -passes=si-wqm -o - %s | FileCheck %s4 5--- |6 define amdgpu_ps void @test_strict_wwm_scc() {7 ret void8 }9 define amdgpu_ps void @test_strict_wwm_scc2() {10 ret void11 }12 define amdgpu_ps void @no_cfg() {13 ret void14 }15 define amdgpu_ps void @copy_exec() {16 ret void17 }18 define amdgpu_ps void @scc_always_live() {19 ret void20 }21 define amdgpu_ps void @test_wwm_set_inactive_propagation() {22 ret void23 }24 define amdgpu_ps void @test_wqm_lr_phi() {25 ret void26 }27 define amdgpu_cs void @no_wqm_in_cs() {28 ret void29 }30 define amdgpu_es void @no_wqm_in_es() {31 ret void32 }33 define amdgpu_gs void @no_wqm_in_gs() {34 ret void35 }36 define amdgpu_hs void @no_wqm_in_hs() {37 ret void38 }39 define amdgpu_ls void @no_wqm_in_ls() {40 ret void41 }42 define amdgpu_vs void @no_wqm_in_vs() {43 ret void44 }45...46---47 48---49# Check for awareness that s_or_saveexec_b64 clobbers SCC50name: test_strict_wwm_scc51alignment: 152exposesReturnsTwice: false53legalized: false54regBankSelected: false55selected: false56tracksRegLiveness: true57registers:58 - { id: 0, class: sgpr_32, preferred-register: '' }59 - { id: 1, class: sgpr_32, preferred-register: '' }60 - { id: 2, class: sgpr_32, preferred-register: '' }61 - { id: 3, class: vgpr_32, preferred-register: '' }62 - { id: 4, class: vgpr_32, preferred-register: '' }63 - { id: 5, class: sgpr_32, preferred-register: '' }64 - { id: 6, class: vgpr_32, preferred-register: '' }65 - { id: 7, class: vgpr_32, preferred-register: '' }66 - { id: 8, class: sreg_32_xm0, preferred-register: '' }67 - { id: 9, class: sreg_32, preferred-register: '' }68 - { id: 10, class: sreg_32, preferred-register: '' }69 - { id: 11, class: vgpr_32, preferred-register: '' }70 - { id: 12, class: vgpr_32, preferred-register: '' }71liveins:72 - { reg: '$sgpr0', virtual-reg: '%0' }73 - { reg: '$sgpr1', virtual-reg: '%1' }74 - { reg: '$sgpr2', virtual-reg: '%2' }75 - { reg: '$vgpr0', virtual-reg: '%3' }76body: |77 bb.0:78 liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr079 80 ; CHECK-LABEL: name: test_strict_wwm_scc81 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr082 ; CHECK-NEXT: {{ $}}83 ; CHECK-NEXT: [[ENTER_STRICT_WWM:%[0-9]+]]:sreg_64 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec84 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr085 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr286 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr187 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr088 ; CHECK-NEXT: S_CMP_LT_I32 0, [[COPY3]], implicit-def $scc89 ; CHECK-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[COPY]], [[COPY]], implicit-def $vcc, implicit $exec90 ; CHECK-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sgpr_32 = S_CSELECT_B32 [[COPY1]], [[COPY2]], implicit $scc91 ; CHECK-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_CSELECT_B32_]], [[V_ADD_CO_U32_e32_]], implicit-def $vcc, implicit $exec92 ; CHECK-NEXT: $exec = EXIT_STRICT_WWM [[ENTER_STRICT_WWM]]93 ; CHECK-NEXT: early-clobber $vgpr0 = V_MOV_B32_e32 [[V_ADD_CO_U32_e32_1]], implicit $exec94 ; CHECK-NEXT: SI_RETURN_TO_EPILOG $vgpr095 %3 = COPY $vgpr096 %2 = COPY $sgpr297 %1 = COPY $sgpr198 %0 = COPY $sgpr099 S_CMP_LT_I32 0, %0, implicit-def $scc100 %12 = V_ADD_CO_U32_e32 %3, %3, implicit-def $vcc, implicit $exec101 %5 = S_CSELECT_B32 %2, %1, implicit $scc102 %11 = V_ADD_CO_U32_e32 %5, %12, implicit-def $vcc, implicit $exec103 $vgpr0 = STRICT_WWM %11, implicit $exec104 SI_RETURN_TO_EPILOG $vgpr0105 106...107 108---109# Second test for awareness that s_or_saveexec_b64 clobbers SCC110# Because entry block is treated differently.111name: test_strict_wwm_scc2112tracksRegLiveness: true113body: |114 ; CHECK-LABEL: name: test_strict_wwm_scc2115 ; CHECK: bb.0:116 ; CHECK-NEXT: successors: %bb.1(0x80000000)117 ; CHECK-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0118 ; CHECK-NEXT: {{ $}}119 ; CHECK-NEXT: [[ENTER_STRICT_WWM:%[0-9]+]]:sreg_64 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec120 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0121 ; CHECK-NEXT: $exec = EXIT_STRICT_WWM [[ENTER_STRICT_WWM]]122 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr2123 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr1124 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr0125 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF126 ; CHECK-NEXT: {{ $}}127 ; CHECK-NEXT: bb.1:128 ; CHECK-NEXT: S_CMP_LT_I32 0, [[COPY3]], implicit-def $scc129 ; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY]], [[DEF]], 0, 0, 0, 0, implicit $exec130 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY $scc131 ; CHECK-NEXT: [[ENTER_STRICT_WWM1:%[0-9]+]]:sreg_64 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec132 ; CHECK-NEXT: $scc = COPY [[COPY4]]133 ; CHECK-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[COPY]], [[COPY]], implicit-def $vcc, implicit $exec134 ; CHECK-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sgpr_32 = S_CSELECT_B32 [[COPY1]], [[COPY2]], implicit $scc135 ; CHECK-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_CSELECT_B32_]], [[V_ADD_CO_U32_e32_]], implicit-def $vcc, implicit $exec136 ; CHECK-NEXT: $exec = EXIT_STRICT_WWM [[ENTER_STRICT_WWM1]]137 ; CHECK-NEXT: early-clobber $vgpr0 = V_MOV_B32_e32 [[V_ADD_CO_U32_e32_1]], implicit $exec138 ; CHECK-NEXT: $vgpr1 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]139 ; CHECK-NEXT: SI_RETURN_TO_EPILOG $vgpr0, $vgpr1140 bb.0:141 liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0142 143 %3:vgpr_32 = COPY $vgpr0144 %2:sgpr_32 = COPY $sgpr2145 %1:sgpr_32 = COPY $sgpr1146 %0:sgpr_32 = COPY $sgpr0147 %13:sgpr_128 = IMPLICIT_DEF148 149 bb.1:150 S_CMP_LT_I32 0, %0:sgpr_32, implicit-def $scc151 %10:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %3:vgpr_32, %13:sgpr_128, 0, 0, 0, 0, implicit $exec152 %12:vgpr_32 = V_ADD_CO_U32_e32 %3:vgpr_32, %3:vgpr_32, implicit-def $vcc, implicit $exec153 %5:sgpr_32 = S_CSELECT_B32 %2:sgpr_32, %1:sgpr_32, implicit $scc154 %11:vgpr_32 = V_ADD_CO_U32_e32 %5:sgpr_32, %12:vgpr_32, implicit-def $vcc, implicit $exec155 $vgpr0 = STRICT_WWM %11:vgpr_32, implicit $exec156 $vgpr1 = COPY %10:vgpr_32157 SI_RETURN_TO_EPILOG $vgpr0, $vgpr1158 159...160 161---162# V_SET_INACTIVE, when its second operand is undef, is replaced by a163# COPY by si-wqm. Ensure the instruction is removed.164name: no_cfg165alignment: 1166exposesReturnsTwice: false167legalized: false168regBankSelected: false169selected: false170failedISel: false171tracksRegLiveness: true172hasWinCFI: false173registers:174 - { id: 0, class: sgpr_32, preferred-register: '' }175 - { id: 1, class: sgpr_32, preferred-register: '' }176 - { id: 2, class: sgpr_32, preferred-register: '' }177 - { id: 3, class: sgpr_32, preferred-register: '' }178 - { id: 4, class: sgpr_32, preferred-register: '' }179 - { id: 5, class: sgpr_128, preferred-register: '' }180 - { id: 6, class: sgpr_128, preferred-register: '' }181 - { id: 7, class: sreg_32, preferred-register: '' }182 - { id: 8, class: vreg_64, preferred-register: '' }183 - { id: 9, class: sreg_32, preferred-register: '' }184 - { id: 10, class: vgpr_32, preferred-register: '' }185 - { id: 11, class: vgpr_32, preferred-register: '' }186 - { id: 12, class: vgpr_32, preferred-register: '' }187 - { id: 13, class: vgpr_32, preferred-register: '' }188 - { id: 14, class: vgpr_32, preferred-register: '' }189 - { id: 15, class: vgpr_32, preferred-register: '' }190 - { id: 16, class: vgpr_32, preferred-register: '' }191liveins:192 - { reg: '$sgpr0', virtual-reg: '%0' }193 - { reg: '$sgpr1', virtual-reg: '%1' }194 - { reg: '$sgpr2', virtual-reg: '%2' }195 - { reg: '$sgpr3', virtual-reg: '%3' }196body: |197 bb.0:198 liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3199 200 ; CHECK-LABEL: name: no_cfg201 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3202 ; CHECK-NEXT: {{ $}}203 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr3204 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr2205 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr1206 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr0207 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY1]], %subreg.sub2, [[COPY]], %subreg.sub3208 ; CHECK-NEXT: dead [[COPY4:%[0-9]+]]:sgpr_128 = COPY [[REG_SEQUENCE]]209 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0210 ; CHECK-NEXT: [[BUFFER_LOAD_DWORDX2_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec211 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFSET]].sub1212 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]213 ; CHECK-NEXT: dead [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF214 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY6]], implicit $exec, implicit-def $scc215 ; CHECK-NEXT: [[ENTER_STRICT_WWM:%[0-9]+]]:sreg_64 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec216 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]217 ; CHECK-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY8]], [[COPY7]], 323, 12, 15, 0, implicit $exec218 ; CHECK-NEXT: $exec = EXIT_STRICT_WWM [[ENTER_STRICT_WWM]]219 ; CHECK-NEXT: early-clobber %15:vgpr_32 = V_MOV_B32_e32 [[V_MOV_B32_dpp]], implicit $exec220 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET_exact %15, [[REG_SEQUENCE]], [[S_MOV_B32_]], 4, 0, 0, implicit $exec221 ; CHECK-NEXT: S_ENDPGM 0222 %3:sgpr_32 = COPY $sgpr3223 %2:sgpr_32 = COPY $sgpr2224 %1:sgpr_32 = COPY $sgpr1225 %0:sgpr_32 = COPY $sgpr0226 %6:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3227 %5:sgpr_128 = COPY %6228 %7:sreg_32 = S_MOV_B32 0229 %8:vreg_64 = BUFFER_LOAD_DWORDX2_OFFSET %6, %7, 0, 0, 0, implicit $exec230 %16:vgpr_32 = COPY %8.sub1231 %11:vgpr_32 = COPY %16232 %17:sreg_64_xexec = IMPLICIT_DEF233 %10:vgpr_32 = V_SET_INACTIVE_B32 0, %11, 0, undef %12, undef %17, implicit $exec, implicit-def $scc234 %14:vgpr_32 = COPY %7235 %13:vgpr_32 = V_MOV_B32_dpp %14, killed %10, 323, 12, 15, 0, implicit $exec236 early-clobber %15:vgpr_32 = STRICT_WWM killed %13, implicit $exec237 BUFFER_STORE_DWORD_OFFSET_exact killed %15, %6, %7, 4, 0, 0, implicit $exec238 S_ENDPGM 0239 240...241 242---243# Ensure that strict_wwm is not put around an EXEC copy244name: copy_exec245tracksRegLiveness: true246body: |247 bb.0:248 liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3249 250 ; CHECK-LABEL: name: copy_exec251 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3252 ; CHECK-NEXT: {{ $}}253 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr3254 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr2255 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr1256 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr0257 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY1]], %subreg.sub2, [[COPY]], %subreg.sub3258 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0259 ; CHECK-NEXT: dead [[BUFFER_LOAD_DWORDX2_OFFSET:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec260 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec261 ; CHECK-NEXT: [[ENTER_STRICT_WWM:%[0-9]+]]:sreg_64 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec262 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec263 ; CHECK-NEXT: $exec = EXIT_STRICT_WWM [[ENTER_STRICT_WWM]]264 ; CHECK-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY4]].sub0, 0, implicit $exec265 ; CHECK-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[V_MOV_B32_e32_]], [[V_MBCNT_LO_U32_B32_e64_]], 312, 15, 15, 0, implicit $exec266 ; CHECK-NEXT: dead [[V_READLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READLANE_B32 [[V_MOV_B32_dpp]], 63267 ; CHECK-NEXT: early-clobber %12:vgpr_32 = V_MOV_B32_e32 [[V_MOV_B32_e32_]], implicit $exec268 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET_exact %12, [[REG_SEQUENCE]], [[S_MOV_B32_]], 4, 0, 0, implicit $exec269 ; CHECK-NEXT: S_ENDPGM 0270 %3:sgpr_32 = COPY $sgpr3271 %2:sgpr_32 = COPY $sgpr2272 %1:sgpr_32 = COPY $sgpr1273 %0:sgpr_32 = COPY $sgpr0274 %4:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3275 %5:sreg_32 = S_MOV_B32 0276 %6:vreg_64 = BUFFER_LOAD_DWORDX2_OFFSET %4, %5, 0, 0, 0, implicit $exec277 278 %8:sreg_64 = COPY $exec279 %9:vgpr_32 = V_MOV_B32_e32 0, implicit $exec280 %10:vgpr_32 = V_MBCNT_LO_U32_B32_e64 %8.sub0:sreg_64, 0, implicit $exec281 %11:vgpr_32 = V_MOV_B32_dpp %9:vgpr_32, %10:vgpr_32, 312, 15, 15, 0, implicit $exec282 %12:sreg_32_xm0 = V_READLANE_B32 %11:vgpr_32, 63283 early-clobber %13:vgpr_32 = STRICT_WWM %9:vgpr_32, implicit $exec284 285 BUFFER_STORE_DWORD_OFFSET_exact killed %13, %4, %5, 4, 0, 0, implicit $exec286 S_ENDPGM 0287 288...289 290---291# Check exit of WQM is still inserted correctly when SCC is live until block end.292# Critially this tests that compilation does not fail.293name: scc_always_live294tracksRegLiveness: true295body: |296 ; CHECK-LABEL: name: scc_always_live297 ; CHECK: bb.0:298 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)299 ; CHECK-NEXT: liveins: $sgpr1, $sgpr2, $vgpr1, $vgpr2300 ; CHECK-NEXT: {{ $}}301 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec302 ; CHECK-NEXT: $m0 = COPY $sgpr1303 ; CHECK-NEXT: $exec = S_WQM_B64 $exec, implicit-def $scc304 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1305 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2306 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr2307 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF308 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF309 ; CHECK-NEXT: [[V_INTERP_P1_F32_:%[0-9]+]]:vgpr_32 = V_INTERP_P1_F32 [[COPY1]], 3, 2, implicit $mode, implicit $m0, implicit $exec310 ; CHECK-NEXT: [[V_INTERP_P1_F32_1:%[0-9]+]]:vgpr_32 = V_INTERP_P1_F32 [[COPY2]], 3, 2, implicit $mode, implicit $m0, implicit $exec311 ; CHECK-NEXT: undef [[COPY4:%[0-9]+]].sub0:vreg_64 = COPY [[V_INTERP_P1_F32_]]312 ; CHECK-NEXT: [[COPY4:%[0-9]+]].sub1:vreg_64 = COPY [[V_INTERP_P1_F32_1]]313 ; CHECK-NEXT: [[IMAGE_SAMPLE_V4_V2_:%[0-9]+]]:vreg_128 = IMAGE_SAMPLE_V4_V2 [[COPY4]], [[DEF]], [[DEF1]], 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)314 ; CHECK-NEXT: S_CMP_EQ_U32 [[COPY3]], 0, implicit-def $scc315 ; CHECK-NEXT: undef [[V_ADD_F32_e64_:%[0-9]+]].sub0:vreg_64 = nsz arcp nofpexcept V_ADD_F32_e64 0, [[IMAGE_SAMPLE_V4_V2_]].sub0, 0, [[V_INTERP_P1_F32_1]], 1, 0, implicit $mode, implicit $exec316 ; CHECK-NEXT: [[V_ADD_F32_e64_:%[0-9]+]].sub1:vreg_64 = nsz arcp nofpexcept V_MUL_F32_e32 [[V_INTERP_P1_F32_]], [[V_INTERP_P1_F32_1]], implicit $mode, implicit $exec317 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32_xm0 = COPY $scc318 ; CHECK-NEXT: $exec = S_AND_B64 $exec, [[COPY]], implicit-def $scc319 ; CHECK-NEXT: $scc = COPY [[COPY5]]320 ; CHECK-NEXT: [[V_ADD_F32_e64_1:%[0-9]+]]:vgpr_32 = nsz arcp nofpexcept V_ADD_F32_e64 0, [[V_INTERP_P1_F32_]], 0, [[V_INTERP_P1_F32_1]], 1, 0, implicit $mode, implicit $exec321 ; CHECK-NEXT: [[IMAGE_SAMPLE_V4_V2_1:%[0-9]+]]:vreg_128 = IMAGE_SAMPLE_V4_V2 [[V_ADD_F32_e64_]], [[DEF]], [[DEF1]], 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)322 ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit $scc323 ; CHECK-NEXT: {{ $}}324 ; CHECK-NEXT: bb.1:325 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0326 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET_exact [[V_ADD_F32_e64_1]], [[DEF1]], [[S_MOV_B32_]], 4, 0, 0, implicit $exec327 ; CHECK-NEXT: S_ENDPGM 0328 ; CHECK-NEXT: {{ $}}329 ; CHECK-NEXT: bb.2:330 ; CHECK-NEXT: $vgpr0 = COPY [[IMAGE_SAMPLE_V4_V2_]].sub0331 ; CHECK-NEXT: $vgpr1 = COPY [[IMAGE_SAMPLE_V4_V2_]].sub1332 ; CHECK-NEXT: $vgpr2 = COPY [[IMAGE_SAMPLE_V4_V2_1]].sub0333 ; CHECK-NEXT: $vgpr3 = COPY [[IMAGE_SAMPLE_V4_V2_1]].sub1334 ; CHECK-NEXT: SI_RETURN_TO_EPILOG $vgpr0, $vgpr1, $vgpr2, $vgpr3335 bb.0:336 liveins: $sgpr1, $sgpr2, $vgpr1, $vgpr2337 338 $m0 = COPY $sgpr1339 %0:vgpr_32 = COPY $vgpr1340 %1:vgpr_32 = COPY $vgpr2341 %8:sgpr_32 = COPY $sgpr2342 %100:sgpr_256 = IMPLICIT_DEF343 %101:sgpr_128 = IMPLICIT_DEF344 345 %2:vgpr_32 = V_INTERP_P1_F32 %0:vgpr_32, 3, 2, implicit $mode, implicit $m0, implicit $exec346 %3:vgpr_32 = V_INTERP_P1_F32 %1:vgpr_32, 3, 2, implicit $mode, implicit $m0, implicit $exec347 348 undef %7.sub0:vreg_64 = COPY %2:vgpr_32349 %7.sub1:vreg_64 = COPY %3:vgpr_32350 351 %4:vreg_128 = IMAGE_SAMPLE_V4_V2 %7:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)352 S_CMP_EQ_U32 %8:sgpr_32, 0, implicit-def $scc353 354 undef %5.sub0:vreg_64 = nsz arcp nofpexcept V_ADD_F32_e64 0, %4.sub0:vreg_128, 0, %3:vgpr_32, 1, 0, implicit $mode, implicit $exec355 %5.sub1:vreg_64 = nsz arcp nofpexcept V_MUL_F32_e32 %2, %3, implicit $mode, implicit $exec356 %6:vgpr_32 = nsz arcp nofpexcept V_ADD_F32_e64 0, %2:vgpr_32, 0, %3:vgpr_32, 1, 0, implicit $mode, implicit $exec357 358 %9:vreg_128 = IMAGE_SAMPLE_V4_V2 %5:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)359 360 S_CBRANCH_SCC0 %bb.2, implicit $scc361 362 bb.1:363 %10:sreg_32 = S_MOV_B32 0364 BUFFER_STORE_DWORD_OFFSET_exact %6:vgpr_32, %101:sgpr_128, %10:sreg_32, 4, 0, 0, implicit $exec365 S_ENDPGM 0366 367 bb.2:368 $vgpr0 = COPY %4.sub0:vreg_128369 $vgpr1 = COPY %4.sub1:vreg_128370 $vgpr2 = COPY %9.sub0:vreg_128371 $vgpr3 = COPY %9.sub1:vreg_128372 SI_RETURN_TO_EPILOG $vgpr0, $vgpr1, $vgpr2, $vgpr3373...374 375---376# Check that unnecessary instruction do not get marked for WWM377#378name: test_wwm_set_inactive_propagation379tracksRegLiveness: true380body: |381 bb.0:382 liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr0383 ; CHECK-LABEL: name: test_wwm_set_inactive_propagation384 ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr0385 ; CHECK-NEXT: {{ $}}386 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3387 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0388 ; CHECK-NEXT: [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN [[COPY1]], [[COPY]], 0, 0, 0, 0, implicit $exec389 ; CHECK-NEXT: [[ENTER_STRICT_WWM:%[0-9]+]]:sreg_64_xexec = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec390 ; CHECK-NEXT: dead [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF391 ; CHECK-NEXT: [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]].sub0:vreg_64 = V_SET_INACTIVE_B32 0, [[BUFFER_LOAD_DWORDX2_OFFEN]].sub0, 0, 0, undef [[ENTER_STRICT_WWM]], implicit $exec, implicit-def $scc392 ; CHECK-NEXT: [[BUFFER_LOAD_DWORDX2_OFFEN:%[0-9]+]].sub1:vreg_64 = V_SET_INACTIVE_B32 0, [[BUFFER_LOAD_DWORDX2_OFFEN]].sub1, 0, 0, undef [[ENTER_STRICT_WWM]], implicit $exec, implicit-def $scc393 ; CHECK-NEXT: [[V_MAX_F64_e64_:%[0-9]+]]:vreg_64 = nnan nsz arcp contract reassoc nofpexcept V_MAX_F64_e64 0, [[BUFFER_LOAD_DWORDX2_OFFEN]], 0, [[BUFFER_LOAD_DWORDX2_OFFEN]], 0, 0, implicit $mode, implicit $exec394 ; CHECK-NEXT: $exec = EXIT_STRICT_WWM [[ENTER_STRICT_WWM]]395 ; CHECK-NEXT: early-clobber $vgpr0 = V_MOV_B32_e32 [[V_MAX_F64_e64_]].sub0, implicit $exec396 ; CHECK-NEXT: early-clobber $vgpr1 = V_MOV_B32_e32 [[V_MAX_F64_e64_]].sub1, implicit $exec397 ; CHECK-NEXT: SI_RETURN_TO_EPILOG $vgpr0, $vgpr1398 %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3399 %1:vgpr_32 = COPY $vgpr0400 %2:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN %1:vgpr_32, %0:sgpr_128, 0, 0, 0, 0, implicit $exec401 %4:sreg_64_xexec = IMPLICIT_DEF402 %2.sub0:vreg_64 = V_SET_INACTIVE_B32 0, %2.sub0:vreg_64, 0, 0, undef %4, implicit $exec, implicit-def $scc403 %2.sub1:vreg_64 = V_SET_INACTIVE_B32 0, %2.sub1:vreg_64, 0, 0, undef %4, implicit $exec, implicit-def $scc404 %3:vreg_64 = nnan nsz arcp contract reassoc nofpexcept V_MAX_F64_e64 0, %2:vreg_64, 0, %2:vreg_64, 0, 0, implicit $mode, implicit $exec405 $vgpr0 = STRICT_WWM %3.sub0:vreg_64, implicit $exec406 $vgpr1 = STRICT_WWM %3.sub1:vreg_64, implicit $exec407 SI_RETURN_TO_EPILOG $vgpr0, $vgpr1408...409 410---411# Check that WQM marking occurs correctly through phi nodes in live range graph.412# If not then initial V_MOV will not be in WQM.413name: test_wqm_lr_phi414tracksRegLiveness: true415body: |416 ; CHECK-LABEL: name: test_wqm_lr_phi417 ; CHECK: bb.0:418 ; CHECK-NEXT: successors: %bb.1(0x80000000)419 ; CHECK-NEXT: {{ $}}420 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec421 ; CHECK-NEXT: $exec = S_WQM_B64 $exec, implicit-def $scc422 ; CHECK-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 -10, implicit $exec423 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec424 ; CHECK-NEXT: [[S_GETPC_B64_:%[0-9]+]]:sreg_64 = S_GETPC_B64425 ; CHECK-NEXT: [[S_LOAD_DWORDX8_IMM:%[0-9]+]]:sgpr_256 = S_LOAD_DWORDX8_IMM [[S_GETPC_B64_]], 32, 0426 ; CHECK-NEXT: {{ $}}427 ; CHECK-NEXT: bb.1:428 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)429 ; CHECK-NEXT: {{ $}}430 ; CHECK-NEXT: $vcc = V_CMP_LT_U32_e64 4, 4, implicit $exec431 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc432 ; CHECK-NEXT: S_BRANCH %bb.2433 ; CHECK-NEXT: {{ $}}434 ; CHECK-NEXT: bb.2:435 ; CHECK-NEXT: successors: %bb.3(0x80000000)436 ; CHECK-NEXT: {{ $}}437 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_ADD_U32_e32 1, [[V_MOV_B32_e32_]].sub1, implicit $exec438 ; CHECK-NEXT: S_BRANCH %bb.3439 ; CHECK-NEXT: {{ $}}440 ; CHECK-NEXT: bb.3:441 ; CHECK-NEXT: successors: %bb.4(0x80000000)442 ; CHECK-NEXT: {{ $}}443 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_ADD_U32_e32 1, [[V_MOV_B32_e32_]].sub1, implicit $exec444 ; CHECK-NEXT: S_BRANCH %bb.4445 ; CHECK-NEXT: {{ $}}446 ; CHECK-NEXT: bb.4:447 ; CHECK-NEXT: $exec = S_AND_B64 $exec, [[COPY]], implicit-def $scc448 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF449 ; CHECK-NEXT: [[IMAGE_SAMPLE_V4_V2_:%[0-9]+]]:vreg_128 = IMAGE_SAMPLE_V4_V2 [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX8_IMM]], [[DEF]], 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)450 ; CHECK-NEXT: $vgpr0 = COPY [[IMAGE_SAMPLE_V4_V2_]].sub0451 ; CHECK-NEXT: $vgpr1 = COPY [[IMAGE_SAMPLE_V4_V2_]].sub1452 ; CHECK-NEXT: SI_RETURN_TO_EPILOG $vgpr0, $vgpr1453 bb.0:454 undef %0.sub0:vreg_64 = V_MOV_B32_e32 -10, implicit $exec455 %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec456 %1:sreg_64 = S_GETPC_B64457 %2:sgpr_256 = S_LOAD_DWORDX8_IMM %1:sreg_64, 32, 0458 459 bb.1:460 $vcc = V_CMP_LT_U32_e64 4, 4, implicit $exec461 S_CBRANCH_VCCNZ %bb.3, implicit $vcc462 S_BRANCH %bb.2463 464 bb.2:465 %0.sub0:vreg_64 = V_ADD_U32_e32 1, %0.sub1, implicit $exec466 S_BRANCH %bb.3467 468 bb.3:469 %0.sub1:vreg_64 = V_ADD_U32_e32 1, %0.sub1, implicit $exec470 S_BRANCH %bb.4471 472 bb.4:473 %3:sgpr_128 = IMPLICIT_DEF474 %4:vreg_128 = IMAGE_SAMPLE_V4_V2 %0:vreg_64, %2:sgpr_256, %3:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)475 $vgpr0 = COPY %4.sub0:vreg_128476 $vgpr1 = COPY %4.sub1:vreg_128477 SI_RETURN_TO_EPILOG $vgpr0, $vgpr1478...479 480---481name: no_wqm_in_cs482tracksRegLiveness: true483body: |484 bb.0:485 liveins: $vgpr1, $vgpr2486 487 ; CHECK-LABEL: name: no_wqm_in_cs488 ; CHECK: liveins: $vgpr1, $vgpr2489 ; CHECK-NEXT: {{ $}}490 ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:vreg_64 = COPY $vgpr1491 ; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY $vgpr2492 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF493 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF494 ; CHECK-NEXT: dead [[IMAGE_SAMPLE_V4_V2_:%[0-9]+]]:vreg_128 = IMAGE_SAMPLE_V4_V2 [[COPY]], [[DEF]], [[DEF1]], 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)495 undef %0.sub0:vreg_64 = COPY $vgpr1496 %0.sub1:vreg_64 = COPY $vgpr2497 %100:sgpr_256 = IMPLICIT_DEF498 %101:sgpr_128 = IMPLICIT_DEF499 500 %4:vreg_128 = IMAGE_SAMPLE_V4_V2 %0:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)501...502 503---504name: no_wqm_in_es505tracksRegLiveness: true506body: |507 bb.0:508 liveins: $vgpr1, $vgpr2509 510 ; CHECK-LABEL: name: no_wqm_in_es511 ; CHECK: liveins: $vgpr1, $vgpr2512 ; CHECK-NEXT: {{ $}}513 ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:vreg_64 = COPY $vgpr1514 ; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY $vgpr2515 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF516 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF517 ; CHECK-NEXT: dead [[IMAGE_SAMPLE_V4_V2_:%[0-9]+]]:vreg_128 = IMAGE_SAMPLE_V4_V2 [[COPY]], [[DEF]], [[DEF1]], 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)518 undef %0.sub0:vreg_64 = COPY $vgpr1519 %0.sub1:vreg_64 = COPY $vgpr2520 %100:sgpr_256 = IMPLICIT_DEF521 %101:sgpr_128 = IMPLICIT_DEF522 523 %4:vreg_128 = IMAGE_SAMPLE_V4_V2 %0:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)524...525 526---527name: no_wqm_in_gs528tracksRegLiveness: true529body: |530 bb.0:531 liveins: $vgpr1, $vgpr2532 533 ; CHECK-LABEL: name: no_wqm_in_gs534 ; CHECK: liveins: $vgpr1, $vgpr2535 ; CHECK-NEXT: {{ $}}536 ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:vreg_64 = COPY $vgpr1537 ; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY $vgpr2538 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF539 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF540 ; CHECK-NEXT: dead [[IMAGE_SAMPLE_V4_V2_:%[0-9]+]]:vreg_128 = IMAGE_SAMPLE_V4_V2 [[COPY]], [[DEF]], [[DEF1]], 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)541 undef %0.sub0:vreg_64 = COPY $vgpr1542 %0.sub1:vreg_64 = COPY $vgpr2543 %100:sgpr_256 = IMPLICIT_DEF544 %101:sgpr_128 = IMPLICIT_DEF545 546 %4:vreg_128 = IMAGE_SAMPLE_V4_V2 %0:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)547...548 549---550name: no_wqm_in_hs551tracksRegLiveness: true552body: |553 bb.0:554 liveins: $vgpr1, $vgpr2555 556 ; CHECK-LABEL: name: no_wqm_in_hs557 ; CHECK: liveins: $vgpr1, $vgpr2558 ; CHECK-NEXT: {{ $}}559 ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:vreg_64 = COPY $vgpr1560 ; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY $vgpr2561 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF562 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF563 ; CHECK-NEXT: dead [[IMAGE_SAMPLE_V4_V2_:%[0-9]+]]:vreg_128 = IMAGE_SAMPLE_V4_V2 [[COPY]], [[DEF]], [[DEF1]], 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)564 undef %0.sub0:vreg_64 = COPY $vgpr1565 %0.sub1:vreg_64 = COPY $vgpr2566 %100:sgpr_256 = IMPLICIT_DEF567 %101:sgpr_128 = IMPLICIT_DEF568 569 %4:vreg_128 = IMAGE_SAMPLE_V4_V2 %0:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)570...571 572---573name: no_wqm_in_ls574tracksRegLiveness: true575body: |576 bb.0:577 liveins: $vgpr1, $vgpr2578 579 ; CHECK-LABEL: name: no_wqm_in_ls580 ; CHECK: liveins: $vgpr1, $vgpr2581 ; CHECK-NEXT: {{ $}}582 ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:vreg_64 = COPY $vgpr1583 ; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY $vgpr2584 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF585 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF586 ; CHECK-NEXT: dead [[IMAGE_SAMPLE_V4_V2_:%[0-9]+]]:vreg_128 = IMAGE_SAMPLE_V4_V2 [[COPY]], [[DEF]], [[DEF1]], 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)587 undef %0.sub0:vreg_64 = COPY $vgpr1588 %0.sub1:vreg_64 = COPY $vgpr2589 %100:sgpr_256 = IMPLICIT_DEF590 %101:sgpr_128 = IMPLICIT_DEF591 592 %4:vreg_128 = IMAGE_SAMPLE_V4_V2 %0:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)593...594 595---596name: no_wqm_in_vs597tracksRegLiveness: true598body: |599 bb.0:600 liveins: $vgpr1, $vgpr2601 602 ; CHECK-LABEL: name: no_wqm_in_vs603 ; CHECK: liveins: $vgpr1, $vgpr2604 ; CHECK-NEXT: {{ $}}605 ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:vreg_64 = COPY $vgpr1606 ; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY $vgpr2607 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF608 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF609 ; CHECK-NEXT: dead [[IMAGE_SAMPLE_V4_V2_:%[0-9]+]]:vreg_128 = IMAGE_SAMPLE_V4_V2 [[COPY]], [[DEF]], [[DEF1]], 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)610 undef %0.sub0:vreg_64 = COPY $vgpr1611 %0.sub1:vreg_64 = COPY $vgpr2612 %100:sgpr_256 = IMPLICIT_DEF613 %101:sgpr_128 = IMPLICIT_DEF614 615 %4:vreg_128 = IMAGE_SAMPLE_V4_V2 %0:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), align 4, addrspace 4)616...617