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1; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck --check-prefix=GCN %s2; RUN: llc -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck --check-prefix=GCN %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck --check-prefix=GCN %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefix=GCN %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck --check-prefix=GCN-DL %s6 7; GCN-LABEL: {{^}}scalar_xnor_i32_one_use8; GCN: s_xnor_b329define amdgpu_kernel void @scalar_xnor_i32_one_use(10 ptr addrspace(1) %r0, i32 %a, i32 %b) {11entry:12 %xor = xor i32 %a, %b13 %r0.val = xor i32 %xor, -114 store i32 %r0.val, ptr addrspace(1) %r015 ret void16}17 18; GCN-LABEL: {{^}}scalar_xnor_i32_mul_use19; GCN-NOT: s_xnor_b3220; GCN: s_xor_b3221; GCN: s_not_b3222; GCN: s_add_i3223define amdgpu_kernel void @scalar_xnor_i32_mul_use(24 ptr addrspace(1) %r0, ptr addrspace(1) %r1, i32 %a, i32 %b) {25entry:26 %xor = xor i32 %a, %b27 %r0.val = xor i32 %xor, -128 %r1.val = add i32 %xor, %a29 store i32 %r0.val, ptr addrspace(1) %r030 store i32 %r1.val, ptr addrspace(1) %r131 ret void32}33 34; GCN-LABEL: {{^}}scalar_xnor_i64_one_use35; GCN: s_xnor_b6436define amdgpu_kernel void @scalar_xnor_i64_one_use(37 ptr addrspace(1) %r0, i64 %a, i64 %b) {38entry:39 %xor = xor i64 %a, %b40 %r0.val = xor i64 %xor, -141 store i64 %r0.val, ptr addrspace(1) %r042 ret void43}44 45; GCN-LABEL: {{^}}scalar_xnor_i64_mul_use46; GCN-NOT: s_xnor_b6447; GCN: s_xor_b6448; GCN: s_not_b6449; GCN: s_add_u3250; GCN: s_addc_u3251define amdgpu_kernel void @scalar_xnor_i64_mul_use(52 ptr addrspace(1) %r0, ptr addrspace(1) %r1, i64 %a, i64 %b) {53entry:54 %xor = xor i64 %a, %b55 %r0.val = xor i64 %xor, -156 %r1.val = add i64 %xor, %a57 store i64 %r0.val, ptr addrspace(1) %r058 store i64 %r1.val, ptr addrspace(1) %r159 ret void60}61 62; GCN-LABEL: {{^}}vector_xnor_i32_one_use63; GCN-NOT: s_xnor_b3264; GCN: v_xor_b3265; GCN: v_not_b3266; GCN-DL: v_xnor_b3267define i32 @vector_xnor_i32_one_use(i32 %a, i32 %b) {68entry:69 %xor = xor i32 %a, %b70 %r = xor i32 %xor, -171 ret i32 %r72}73 74; GCN-LABEL: {{^}}vector_xnor_i64_one_use75; GCN-NOT: s_xnor_b6476; GCN: v_xor_b3277; GCN: v_xor_b3278; GCN: v_not_b3279; GCN: v_not_b3280; GCN-DL: v_xnor_b3281; GCN-DL: v_xnor_b3282define i64 @vector_xnor_i64_one_use(i64 %a, i64 %b) {83entry:84 %xor = xor i64 %a, %b85 %r = xor i64 %xor, -186 ret i64 %r87}88 89; GCN-LABEL: {{^}}xnor_s_v_i32_one_use90; GCN-NOT: s_xnor_b3291; GCN: s_not_b3292; GCN: v_xor_b3293define amdgpu_kernel void @xnor_s_v_i32_one_use(ptr addrspace(1) %out, i32 %s) {94 %v = call i32 @llvm.amdgcn.workitem.id.x() #195 %xor = xor i32 %s, %v96 %d = xor i32 %xor, -197 store i32 %d, ptr addrspace(1) %out98 ret void99}100 101; GCN-LABEL: {{^}}xnor_v_s_i32_one_use102; GCN-NOT: s_xnor_b32103; GCN: s_not_b32104; GCN: v_xor_b32105define amdgpu_kernel void @xnor_v_s_i32_one_use(ptr addrspace(1) %out, i32 %s) {106 %v = call i32 @llvm.amdgcn.workitem.id.x() #1107 %xor = xor i32 %v, %s108 %d = xor i32 %xor, -1109 store i32 %d, ptr addrspace(1) %out110 ret void111}112 113; GCN-LABEL: {{^}}xnor_i64_s_v_one_use114; GCN-NOT: s_xnor_b64115; GCN: s_not_b64116; GCN: v_xor_b32_e32117; GCN-DL: v_xnor_b32118; GCN-DL: v_xnor_b32119define amdgpu_kernel void @xnor_i64_s_v_one_use(120 ptr addrspace(1) %r0, i64 %a) {121entry:122 %b32 = call i32 @llvm.amdgcn.workitem.id.x() #1123 %b64 = zext i32 %b32 to i64124 %b = shl i64 %b64, 29125 %xor = xor i64 %a, %b126 %r0.val = xor i64 %xor, -1127 store i64 %r0.val, ptr addrspace(1) %r0128 ret void129}130 131; GCN-LABEL: {{^}}xnor_i64_v_s_one_use132; GCN-NOT: s_xnor_b64133; GCN: s_not_b64134; GCN: v_xor_b32_e32135; GCN-DL: v_xnor_b32136; GCN-DL: v_xnor_b32137define amdgpu_kernel void @xnor_i64_v_s_one_use(138 ptr addrspace(1) %r0, i64 %a) {139entry:140 %b32 = call i32 @llvm.amdgcn.workitem.id.x() #1141 %b64 = zext i32 %b32 to i64142 %b = shl i64 %b64, 29143 %xor = xor i64 %b, %a144 %r0.val = xor i64 %xor, -1145 store i64 %r0.val, ptr addrspace(1) %r0146 ret void147}148 149; GCN-LABEL: {{^}}vector_xor_na_b_i32_one_use150; GCN-NOT: s_xnor_b32151; GCN: v_xor_b32152; GCN: v_not_b32153; GCN-DL: v_xnor_b32154define i32 @vector_xor_na_b_i32_one_use(i32 %a, i32 %b) {155entry:156 %na = xor i32 %a, -1157 %r = xor i32 %na, %b158 ret i32 %r159}160 161; GCN-LABEL: {{^}}vector_xor_a_nb_i32_one_use162; GCN-NOT: s_xnor_b32163; GCN: v_xor_b32164; GCN: v_not_b32165; GCN-DL: v_xnor_b32166define i32 @vector_xor_a_nb_i32_one_use(i32 %a, i32 %b) {167entry:168 %nb = xor i32 %b, -1169 %r = xor i32 %a, %nb170 ret i32 %r171}172 173; GCN-LABEL: {{^}}scalar_xor_a_nb_i64_one_use174; GCN: s_xnor_b64175define amdgpu_kernel void @scalar_xor_a_nb_i64_one_use(176 ptr addrspace(1) %r0, i64 %a, i64 %b) {177entry:178 %nb = xor i64 %b, -1179 %r0.val = xor i64 %a, %nb180 store i64 %r0.val, ptr addrspace(1) %r0181 ret void182}183 184; GCN-LABEL: {{^}}scalar_xor_na_b_i64_one_use185; GCN: s_xnor_b64186define amdgpu_kernel void @scalar_xor_na_b_i64_one_use(187 ptr addrspace(1) %r0, i64 %a, i64 %b) {188entry:189 %na = xor i64 %a, -1190 %r0.val = xor i64 %na, %b191 store i64 %r0.val, ptr addrspace(1) %r0192 ret void193}194 195; Function Attrs: nounwind readnone196declare i32 @llvm.amdgcn.workitem.id.x() #0197