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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=verde < %s | FileCheck -enable-var-scope -check-prefixes=SI %s3; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefixes=VI %s4 5define amdgpu_ps <2 x i32> @s_xor_v2i32(<2 x i32> inreg %num, <2 x i32> inreg %den) {6; SI-LABEL: s_xor_v2i32:7; SI: ; %bb.0:8; SI-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]9; SI-NEXT: ; return to shader part epilog10;11; VI-LABEL: s_xor_v2i32:12; VI: ; %bb.0:13; VI-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]14; VI-NEXT: ; return to shader part epilog15 %result = xor <2 x i32> %num, %den16 ret <2 x i32> %result17}18 19define <2 x i32> @v_xor_v2i32(<2 x i32> %num, <2 x i32> %den) {20; SI-LABEL: v_xor_v2i32:21; SI: ; %bb.0:22; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)23; SI-NEXT: v_xor_b32_e32 v1, v1, v324; SI-NEXT: v_xor_b32_e32 v0, v0, v225; SI-NEXT: s_setpc_b64 s[30:31]26;27; VI-LABEL: v_xor_v2i32:28; VI: ; %bb.0:29; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)30; VI-NEXT: v_xor_b32_e32 v1, v1, v331; VI-NEXT: v_xor_b32_e32 v0, v0, v232; VI-NEXT: s_setpc_b64 s[30:31]33 %result = xor <2 x i32> %num, %den34 ret <2 x i32> %result35}36 37define amdgpu_kernel void @xor_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {38; SI-LABEL: xor_v2i32:39; SI: ; %bb.0:40; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x941; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd42; SI-NEXT: s_mov_b32 s7, 0xf00043; SI-NEXT: s_mov_b32 s6, -144; SI-NEXT: s_mov_b32 s10, s645; SI-NEXT: s_mov_b32 s11, s746; SI-NEXT: s_waitcnt lgkmcnt(0)47; SI-NEXT: s_mov_b32 s12, s248; SI-NEXT: s_mov_b32 s13, s349; SI-NEXT: s_mov_b32 s14, s650; SI-NEXT: s_mov_b32 s15, s751; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 052; SI-NEXT: buffer_load_dwordx2 v[2:3], off, s[12:15], 053; SI-NEXT: s_mov_b32 s4, s054; SI-NEXT: s_mov_b32 s5, s155; SI-NEXT: s_waitcnt vmcnt(0)56; SI-NEXT: v_xor_b32_e32 v0, v2, v057; SI-NEXT: v_xor_b32_e32 v1, v3, v158; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 059; SI-NEXT: s_endpgm60;61; VI-LABEL: xor_v2i32:62; VI: ; %bb.0:63; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2464; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x3465; VI-NEXT: s_waitcnt lgkmcnt(0)66; VI-NEXT: v_mov_b32_e32 v0, s267; VI-NEXT: v_mov_b32_e32 v1, s368; VI-NEXT: v_mov_b32_e32 v2, s469; VI-NEXT: v_mov_b32_e32 v3, s570; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]71; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]72; VI-NEXT: v_mov_b32_e32 v4, s073; VI-NEXT: v_mov_b32_e32 v5, s174; VI-NEXT: s_waitcnt vmcnt(0)75; VI-NEXT: v_xor_b32_e32 v0, v0, v276; VI-NEXT: v_xor_b32_e32 v1, v1, v377; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]78; VI-NEXT: s_endpgm79 80 %a = load <2 x i32>, ptr addrspace(1) %in081 %b = load <2 x i32>, ptr addrspace(1) %in182 %result = xor <2 x i32> %a, %b83 store <2 x i32> %result, ptr addrspace(1) %out84 ret void85}86 87define amdgpu_kernel void @xor_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {88; SI-LABEL: xor_v4i32:89; SI: ; %bb.0:90; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x991; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd92; SI-NEXT: s_mov_b32 s7, 0xf00093; SI-NEXT: s_mov_b32 s6, -194; SI-NEXT: s_mov_b32 s10, s695; SI-NEXT: s_mov_b32 s11, s796; SI-NEXT: s_waitcnt lgkmcnt(0)97; SI-NEXT: s_mov_b32 s12, s298; SI-NEXT: s_mov_b32 s13, s399; SI-NEXT: s_mov_b32 s14, s6100; SI-NEXT: s_mov_b32 s15, s7101; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0102; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[12:15], 0103; SI-NEXT: s_mov_b32 s4, s0104; SI-NEXT: s_mov_b32 s5, s1105; SI-NEXT: s_waitcnt vmcnt(0)106; SI-NEXT: v_xor_b32_e32 v3, v7, v3107; SI-NEXT: v_xor_b32_e32 v2, v6, v2108; SI-NEXT: v_xor_b32_e32 v1, v5, v1109; SI-NEXT: v_xor_b32_e32 v0, v4, v0110; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0111; SI-NEXT: s_endpgm112;113; VI-LABEL: xor_v4i32:114; VI: ; %bb.0:115; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24116; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34117; VI-NEXT: s_waitcnt lgkmcnt(0)118; VI-NEXT: v_mov_b32_e32 v0, s2119; VI-NEXT: v_mov_b32_e32 v1, s3120; VI-NEXT: v_mov_b32_e32 v4, s4121; VI-NEXT: v_mov_b32_e32 v5, s5122; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]123; VI-NEXT: flat_load_dwordx4 v[4:7], v[4:5]124; VI-NEXT: v_mov_b32_e32 v8, s0125; VI-NEXT: v_mov_b32_e32 v9, s1126; VI-NEXT: s_waitcnt vmcnt(0)127; VI-NEXT: v_xor_b32_e32 v3, v3, v7128; VI-NEXT: v_xor_b32_e32 v2, v2, v6129; VI-NEXT: v_xor_b32_e32 v1, v1, v5130; VI-NEXT: v_xor_b32_e32 v0, v0, v4131; VI-NEXT: flat_store_dwordx4 v[8:9], v[0:3]132; VI-NEXT: s_endpgm133 %a = load <4 x i32>, ptr addrspace(1) %in0134 %b = load <4 x i32>, ptr addrspace(1) %in1135 %result = xor <4 x i32> %a, %b136 store <4 x i32> %result, ptr addrspace(1) %out137 ret void138}139 140define amdgpu_kernel void @xor_i1(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {141; SI-LABEL: xor_i1:142; SI: ; %bb.0:143; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9144; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd145; SI-NEXT: s_mov_b32 s7, 0xf000146; SI-NEXT: s_mov_b32 s6, -1147; SI-NEXT: s_mov_b32 s10, s6148; SI-NEXT: s_mov_b32 s11, s7149; SI-NEXT: s_waitcnt lgkmcnt(0)150; SI-NEXT: s_mov_b32 s12, s2151; SI-NEXT: s_mov_b32 s13, s3152; SI-NEXT: s_mov_b32 s14, s6153; SI-NEXT: s_mov_b32 s15, s7154; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0155; SI-NEXT: buffer_load_dword v1, off, s[12:15], 0156; SI-NEXT: s_mov_b32 s4, s0157; SI-NEXT: s_mov_b32 s5, s1158; SI-NEXT: s_waitcnt vmcnt(1)159; SI-NEXT: v_cmp_le_f32_e32 vcc, 1.0, v0160; SI-NEXT: s_waitcnt vmcnt(0)161; SI-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1162; SI-NEXT: s_xor_b64 vcc, s[0:1], vcc163; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc164; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0165; SI-NEXT: s_endpgm166;167; VI-LABEL: xor_i1:168; VI: ; %bb.0:169; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24170; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34171; VI-NEXT: s_waitcnt lgkmcnt(0)172; VI-NEXT: v_mov_b32_e32 v0, s2173; VI-NEXT: v_mov_b32_e32 v1, s3174; VI-NEXT: v_mov_b32_e32 v2, s4175; VI-NEXT: v_mov_b32_e32 v3, s5176; VI-NEXT: flat_load_dword v4, v[0:1]177; VI-NEXT: flat_load_dword v2, v[2:3]178; VI-NEXT: v_mov_b32_e32 v0, s0179; VI-NEXT: v_mov_b32_e32 v1, s1180; VI-NEXT: s_waitcnt vmcnt(1)181; VI-NEXT: v_cmp_le_f32_e32 vcc, 0, v4182; VI-NEXT: s_waitcnt vmcnt(0)183; VI-NEXT: v_cmp_le_f32_e64 s[0:1], 1.0, v2184; VI-NEXT: s_xor_b64 vcc, vcc, s[0:1]185; VI-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc186; VI-NEXT: flat_store_dword v[0:1], v2187; VI-NEXT: s_endpgm188 189 %a = load float, ptr addrspace(1) %in0190 %b = load float, ptr addrspace(1) %in1191 %acmp = fcmp oge float %a, 0.000000e+00192 %bcmp = fcmp oge float %b, 1.000000e+00193 %xor = xor i1 %acmp, %bcmp194 %result = select i1 %xor, float %a, float %b195 store float %result, ptr addrspace(1) %out196 ret void197}198 199define amdgpu_kernel void @v_xor_i1(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {200; SI-LABEL: v_xor_i1:201; SI: ; %bb.0:202; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9203; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd204; SI-NEXT: s_mov_b32 s7, 0xf000205; SI-NEXT: s_mov_b32 s6, -1206; SI-NEXT: s_mov_b32 s14, s6207; SI-NEXT: s_waitcnt lgkmcnt(0)208; SI-NEXT: s_mov_b32 s12, s2209; SI-NEXT: s_mov_b32 s13, s3210; SI-NEXT: s_mov_b32 s15, s7211; SI-NEXT: s_mov_b32 s10, s6212; SI-NEXT: s_mov_b32 s11, s7213; SI-NEXT: buffer_load_ubyte v0, off, s[12:15], 0 glc214; SI-NEXT: s_waitcnt vmcnt(0)215; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 glc216; SI-NEXT: s_waitcnt vmcnt(0)217; SI-NEXT: s_mov_b32 s4, s0218; SI-NEXT: s_mov_b32 s5, s1219; SI-NEXT: v_xor_b32_e32 v0, v0, v1220; SI-NEXT: v_and_b32_e32 v0, 1, v0221; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0222; SI-NEXT: s_endpgm223;224; VI-LABEL: v_xor_i1:225; VI: ; %bb.0:226; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24227; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34228; VI-NEXT: s_waitcnt lgkmcnt(0)229; VI-NEXT: v_mov_b32_e32 v0, s2230; VI-NEXT: v_mov_b32_e32 v1, s3231; VI-NEXT: v_mov_b32_e32 v2, s4232; VI-NEXT: v_mov_b32_e32 v3, s5233; VI-NEXT: flat_load_ubyte v4, v[0:1] glc234; VI-NEXT: s_waitcnt vmcnt(0)235; VI-NEXT: flat_load_ubyte v2, v[2:3] glc236; VI-NEXT: s_waitcnt vmcnt(0)237; VI-NEXT: v_mov_b32_e32 v0, s0238; VI-NEXT: v_mov_b32_e32 v1, s1239; VI-NEXT: v_xor_b32_e32 v2, v4, v2240; VI-NEXT: v_and_b32_e32 v2, 1, v2241; VI-NEXT: flat_store_byte v[0:1], v2242; VI-NEXT: s_endpgm243 %a = load volatile i1, ptr addrspace(1) %in0244 %b = load volatile i1, ptr addrspace(1) %in1245 %xor = xor i1 %a, %b246 store i1 %xor, ptr addrspace(1) %out247 ret void248}249 250define amdgpu_kernel void @vector_xor_i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {251; SI-LABEL: vector_xor_i32:252; SI: ; %bb.0:253; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9254; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd255; SI-NEXT: s_mov_b32 s7, 0xf000256; SI-NEXT: s_mov_b32 s6, -1257; SI-NEXT: s_mov_b32 s14, s6258; SI-NEXT: s_waitcnt lgkmcnt(0)259; SI-NEXT: s_mov_b32 s12, s2260; SI-NEXT: s_mov_b32 s13, s3261; SI-NEXT: s_mov_b32 s15, s7262; SI-NEXT: s_mov_b32 s10, s6263; SI-NEXT: s_mov_b32 s11, s7264; SI-NEXT: buffer_load_dword v0, off, s[12:15], 0265; SI-NEXT: buffer_load_dword v1, off, s[8:11], 0266; SI-NEXT: s_mov_b32 s4, s0267; SI-NEXT: s_mov_b32 s5, s1268; SI-NEXT: s_waitcnt vmcnt(0)269; SI-NEXT: v_xor_b32_e32 v0, v0, v1270; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0271; SI-NEXT: s_endpgm272;273; VI-LABEL: vector_xor_i32:274; VI: ; %bb.0:275; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24276; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34277; VI-NEXT: s_waitcnt lgkmcnt(0)278; VI-NEXT: v_mov_b32_e32 v0, s2279; VI-NEXT: v_mov_b32_e32 v1, s3280; VI-NEXT: v_mov_b32_e32 v2, s4281; VI-NEXT: v_mov_b32_e32 v3, s5282; VI-NEXT: flat_load_dword v4, v[0:1]283; VI-NEXT: flat_load_dword v2, v[2:3]284; VI-NEXT: v_mov_b32_e32 v0, s0285; VI-NEXT: v_mov_b32_e32 v1, s1286; VI-NEXT: s_waitcnt vmcnt(0)287; VI-NEXT: v_xor_b32_e32 v2, v4, v2288; VI-NEXT: flat_store_dword v[0:1], v2289; VI-NEXT: s_endpgm290 %a = load i32, ptr addrspace(1) %in0291 %b = load i32, ptr addrspace(1) %in1292 %result = xor i32 %a, %b293 store i32 %result, ptr addrspace(1) %out294 ret void295}296 297define amdgpu_kernel void @scalar_xor_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {298; SI-LABEL: scalar_xor_i32:299; SI: ; %bb.0:300; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9301; SI-NEXT: s_waitcnt lgkmcnt(0)302; SI-NEXT: s_mov_b64 s[4:5], s[2:3]303; SI-NEXT: s_xor_b32 s4, s4, s5304; SI-NEXT: s_mov_b32 s3, 0xf000305; SI-NEXT: s_mov_b32 s2, -1306; SI-NEXT: v_mov_b32_e32 v0, s4307; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0308; SI-NEXT: s_endpgm309;310; VI-LABEL: scalar_xor_i32:311; VI: ; %bb.0:312; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24313; VI-NEXT: s_waitcnt lgkmcnt(0)314; VI-NEXT: s_xor_b32 s2, s2, s3315; VI-NEXT: v_mov_b32_e32 v0, s0316; VI-NEXT: v_mov_b32_e32 v1, s1317; VI-NEXT: v_mov_b32_e32 v2, s2318; VI-NEXT: flat_store_dword v[0:1], v2319; VI-NEXT: s_endpgm320 %result = xor i32 %a, %b321 store i32 %result, ptr addrspace(1) %out322 ret void323}324 325define amdgpu_kernel void @scalar_not_i32(ptr addrspace(1) %out, i32 %a) {326; SI-LABEL: scalar_not_i32:327; SI: ; %bb.0:328; SI-NEXT: s_load_dword s6, s[4:5], 0xb329; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9330; SI-NEXT: s_mov_b32 s3, 0xf000331; SI-NEXT: s_mov_b32 s2, -1332; SI-NEXT: s_waitcnt lgkmcnt(0)333; SI-NEXT: s_not_b32 s4, s6334; SI-NEXT: v_mov_b32_e32 v0, s4335; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0336; SI-NEXT: s_endpgm337;338; VI-LABEL: scalar_not_i32:339; VI: ; %bb.0:340; VI-NEXT: s_load_dword s2, s[4:5], 0x2c341; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24342; VI-NEXT: s_waitcnt lgkmcnt(0)343; VI-NEXT: s_not_b32 s2, s2344; VI-NEXT: v_mov_b32_e32 v0, s0345; VI-NEXT: v_mov_b32_e32 v1, s1346; VI-NEXT: v_mov_b32_e32 v2, s2347; VI-NEXT: flat_store_dword v[0:1], v2348; VI-NEXT: s_endpgm349 %result = xor i32 %a, -1350 store i32 %result, ptr addrspace(1) %out351 ret void352}353 354define amdgpu_kernel void @vector_not_i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {355; SI-LABEL: vector_not_i32:356; SI: ; %bb.0:357; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9358; SI-NEXT: s_mov_b32 s7, 0xf000359; SI-NEXT: s_mov_b32 s6, -1360; SI-NEXT: s_mov_b32 s10, s6361; SI-NEXT: s_mov_b32 s11, s7362; SI-NEXT: s_waitcnt lgkmcnt(0)363; SI-NEXT: s_mov_b32 s8, s2364; SI-NEXT: s_mov_b32 s9, s3365; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0366; SI-NEXT: s_mov_b32 s4, s0367; SI-NEXT: s_mov_b32 s5, s1368; SI-NEXT: s_waitcnt vmcnt(0)369; SI-NEXT: v_not_b32_e32 v0, v0370; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0371; SI-NEXT: s_endpgm372;373; VI-LABEL: vector_not_i32:374; VI: ; %bb.0:375; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24376; VI-NEXT: s_waitcnt lgkmcnt(0)377; VI-NEXT: v_mov_b32_e32 v0, s2378; VI-NEXT: v_mov_b32_e32 v1, s3379; VI-NEXT: flat_load_dword v2, v[0:1]380; VI-NEXT: v_mov_b32_e32 v0, s0381; VI-NEXT: v_mov_b32_e32 v1, s1382; VI-NEXT: s_waitcnt vmcnt(0)383; VI-NEXT: v_not_b32_e32 v2, v2384; VI-NEXT: flat_store_dword v[0:1], v2385; VI-NEXT: s_endpgm386 %a = load i32, ptr addrspace(1) %in0387 %b = load i32, ptr addrspace(1) %in1388 %result = xor i32 %a, -1389 store i32 %result, ptr addrspace(1) %out390 ret void391}392 393define amdgpu_kernel void @vector_xor_i64(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {394; SI-LABEL: vector_xor_i64:395; SI: ; %bb.0:396; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9397; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd398; SI-NEXT: s_mov_b32 s7, 0xf000399; SI-NEXT: s_mov_b32 s6, -1400; SI-NEXT: s_mov_b32 s10, s6401; SI-NEXT: s_mov_b32 s11, s7402; SI-NEXT: s_waitcnt lgkmcnt(0)403; SI-NEXT: s_mov_b32 s12, s2404; SI-NEXT: s_mov_b32 s13, s3405; SI-NEXT: s_mov_b32 s14, s6406; SI-NEXT: s_mov_b32 s15, s7407; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0408; SI-NEXT: buffer_load_dwordx2 v[2:3], off, s[12:15], 0409; SI-NEXT: s_mov_b32 s4, s0410; SI-NEXT: s_mov_b32 s5, s1411; SI-NEXT: s_waitcnt vmcnt(0)412; SI-NEXT: v_xor_b32_e32 v0, v2, v0413; SI-NEXT: v_xor_b32_e32 v1, v3, v1414; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0415; SI-NEXT: s_endpgm416;417; VI-LABEL: vector_xor_i64:418; VI: ; %bb.0:419; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24420; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34421; VI-NEXT: s_waitcnt lgkmcnt(0)422; VI-NEXT: v_mov_b32_e32 v0, s2423; VI-NEXT: v_mov_b32_e32 v1, s3424; VI-NEXT: v_mov_b32_e32 v2, s4425; VI-NEXT: v_mov_b32_e32 v3, s5426; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]427; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]428; VI-NEXT: v_mov_b32_e32 v4, s0429; VI-NEXT: v_mov_b32_e32 v5, s1430; VI-NEXT: s_waitcnt vmcnt(0)431; VI-NEXT: v_xor_b32_e32 v0, v0, v2432; VI-NEXT: v_xor_b32_e32 v1, v1, v3433; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]434; VI-NEXT: s_endpgm435 %a = load i64, ptr addrspace(1) %in0436 %b = load i64, ptr addrspace(1) %in1437 %result = xor i64 %a, %b438 store i64 %result, ptr addrspace(1) %out439 ret void440}441 442define amdgpu_kernel void @scalar_xor_i64(ptr addrspace(1) %out, i64 %a, i64 %b) {443; SI-LABEL: scalar_xor_i64:444; SI: ; %bb.0:445; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9446; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd447; SI-NEXT: s_mov_b32 s7, 0xf000448; SI-NEXT: s_mov_b32 s6, -1449; SI-NEXT: s_waitcnt lgkmcnt(0)450; SI-NEXT: s_mov_b32 s4, s0451; SI-NEXT: s_mov_b32 s5, s1452; SI-NEXT: s_xor_b64 s[0:1], s[2:3], s[8:9]453; SI-NEXT: v_mov_b32_e32 v0, s0454; SI-NEXT: v_mov_b32_e32 v1, s1455; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0456; SI-NEXT: s_endpgm457;458; VI-LABEL: scalar_xor_i64:459; VI: ; %bb.0:460; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24461; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34462; VI-NEXT: s_waitcnt lgkmcnt(0)463; VI-NEXT: v_mov_b32_e32 v0, s0464; VI-NEXT: v_mov_b32_e32 v1, s1465; VI-NEXT: s_xor_b64 s[0:1], s[2:3], s[4:5]466; VI-NEXT: v_mov_b32_e32 v3, s1467; VI-NEXT: v_mov_b32_e32 v2, s0468; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]469; VI-NEXT: s_endpgm470 %result = xor i64 %a, %b471 store i64 %result, ptr addrspace(1) %out472 ret void473}474 475define amdgpu_kernel void @scalar_not_i64(ptr addrspace(1) %out, i64 %a) {476; SI-LABEL: scalar_not_i64:477; SI: ; %bb.0:478; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9479; SI-NEXT: s_mov_b32 s7, 0xf000480; SI-NEXT: s_mov_b32 s6, -1481; SI-NEXT: s_waitcnt lgkmcnt(0)482; SI-NEXT: s_mov_b32 s4, s0483; SI-NEXT: s_mov_b32 s5, s1484; SI-NEXT: s_not_b64 s[0:1], s[2:3]485; SI-NEXT: v_mov_b32_e32 v0, s0486; SI-NEXT: v_mov_b32_e32 v1, s1487; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0488; SI-NEXT: s_endpgm489;490; VI-LABEL: scalar_not_i64:491; VI: ; %bb.0:492; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24493; VI-NEXT: s_waitcnt lgkmcnt(0)494; VI-NEXT: v_mov_b32_e32 v0, s0495; VI-NEXT: v_mov_b32_e32 v1, s1496; VI-NEXT: s_not_b64 s[0:1], s[2:3]497; VI-NEXT: v_mov_b32_e32 v3, s1498; VI-NEXT: v_mov_b32_e32 v2, s0499; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]500; VI-NEXT: s_endpgm501 %result = xor i64 %a, -1502 store i64 %result, ptr addrspace(1) %out503 ret void504}505 506define amdgpu_kernel void @vector_not_i64(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {507; SI-LABEL: vector_not_i64:508; SI: ; %bb.0:509; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9510; SI-NEXT: s_mov_b32 s7, 0xf000511; SI-NEXT: s_mov_b32 s6, -1512; SI-NEXT: s_mov_b32 s10, s6513; SI-NEXT: s_mov_b32 s11, s7514; SI-NEXT: s_waitcnt lgkmcnt(0)515; SI-NEXT: s_mov_b32 s8, s2516; SI-NEXT: s_mov_b32 s9, s3517; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0518; SI-NEXT: s_mov_b32 s4, s0519; SI-NEXT: s_mov_b32 s5, s1520; SI-NEXT: s_waitcnt vmcnt(0)521; SI-NEXT: v_not_b32_e32 v0, v0522; SI-NEXT: v_not_b32_e32 v1, v1523; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0524; SI-NEXT: s_endpgm525;526; VI-LABEL: vector_not_i64:527; VI: ; %bb.0:528; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24529; VI-NEXT: s_waitcnt lgkmcnt(0)530; VI-NEXT: v_mov_b32_e32 v0, s2531; VI-NEXT: v_mov_b32_e32 v1, s3532; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]533; VI-NEXT: v_mov_b32_e32 v2, s0534; VI-NEXT: v_mov_b32_e32 v3, s1535; VI-NEXT: s_waitcnt vmcnt(0)536; VI-NEXT: v_not_b32_e32 v0, v0537; VI-NEXT: v_not_b32_e32 v1, v1538; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]539; VI-NEXT: s_endpgm540 %a = load i64, ptr addrspace(1) %in0541 %b = load i64, ptr addrspace(1) %in1542 %result = xor i64 %a, -1543 store i64 %result, ptr addrspace(1) %out544 ret void545}546 547define amdgpu_kernel void @xor_cf(ptr addrspace(1) %out, ptr addrspace(1) %in, i64 %a, i64 %b) {548; SI-LABEL: xor_cf:549; SI: ; %bb.0: ; %entry550; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9551; SI-NEXT: s_mov_b64 s[8:9], 0552; SI-NEXT: s_waitcnt lgkmcnt(0)553; SI-NEXT: v_cmp_ne_u64_e64 s[10:11], s[4:5], 0554; SI-NEXT: s_and_b64 vcc, exec, s[10:11]555; SI-NEXT: s_cbranch_vccz .LBB14_4556; SI-NEXT: ; %bb.1: ; %else557; SI-NEXT: s_mov_b32 s15, 0xf000558; SI-NEXT: s_mov_b32 s14, -1559; SI-NEXT: s_mov_b32 s12, s2560; SI-NEXT: s_mov_b32 s13, s3561; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[12:15], 0562; SI-NEXT: s_andn2_b64 vcc, exec, s[8:9]563; SI-NEXT: s_cbranch_vccnz .LBB14_3564; SI-NEXT: .LBB14_2: ; %if565; SI-NEXT: s_xor_b64 s[2:3], s[4:5], s[6:7]566; SI-NEXT: s_waitcnt vmcnt(0)567; SI-NEXT: v_mov_b32_e32 v0, s2568; SI-NEXT: v_mov_b32_e32 v1, s3569; SI-NEXT: .LBB14_3: ; %endif570; SI-NEXT: s_mov_b32 s3, 0xf000571; SI-NEXT: s_mov_b32 s2, -1572; SI-NEXT: s_waitcnt vmcnt(0)573; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0574; SI-NEXT: s_endpgm575; SI-NEXT: .LBB14_4:576; SI-NEXT: ; implicit-def: $vgpr0_vgpr1577; SI-NEXT: s_branch .LBB14_2578;579; VI-LABEL: xor_cf:580; VI: ; %bb.0: ; %entry581; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24582; VI-NEXT: s_mov_b64 s[8:9], 0583; VI-NEXT: s_waitcnt lgkmcnt(0)584; VI-NEXT: s_cmp_lg_u64 s[4:5], 0585; VI-NEXT: s_cbranch_scc0 .LBB14_4586; VI-NEXT: ; %bb.1: ; %else587; VI-NEXT: v_mov_b32_e32 v0, s2588; VI-NEXT: v_mov_b32_e32 v1, s3589; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]590; VI-NEXT: s_andn2_b64 vcc, exec, s[8:9]591; VI-NEXT: s_cbranch_vccnz .LBB14_3592; VI-NEXT: .LBB14_2: ; %if593; VI-NEXT: s_xor_b64 s[2:3], s[4:5], s[6:7]594; VI-NEXT: s_waitcnt vmcnt(0)595; VI-NEXT: v_mov_b32_e32 v0, s2596; VI-NEXT: v_mov_b32_e32 v1, s3597; VI-NEXT: .LBB14_3: ; %endif598; VI-NEXT: v_mov_b32_e32 v2, s0599; VI-NEXT: v_mov_b32_e32 v3, s1600; VI-NEXT: s_waitcnt vmcnt(0)601; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]602; VI-NEXT: s_endpgm603; VI-NEXT: .LBB14_4:604; VI-NEXT: ; implicit-def: $vgpr0_vgpr1605; VI-NEXT: s_branch .LBB14_2606entry:607 %0 = icmp eq i64 %a, 0608 br i1 %0, label %if, label %else609 610if:611 %1 = xor i64 %a, %b612 br label %endif613 614else:615 %2 = load i64, ptr addrspace(1) %in616 br label %endif617 618endif:619 %3 = phi i64 [%1, %if], [%2, %else]620 store i64 %3, ptr addrspace(1) %out621 ret void622}623 624define amdgpu_kernel void @scalar_xor_literal_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {625; SI-LABEL: scalar_xor_literal_i64:626; SI: ; %bb.0:627; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x13628; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9629; SI-NEXT: s_mov_b32 s3, 0xf000630; SI-NEXT: s_mov_b32 s2, -1631; SI-NEXT: s_waitcnt lgkmcnt(0)632; SI-NEXT: s_xor_b32 s4, s7, 0xf237b633; SI-NEXT: s_xor_b32 s5, s6, 0x3039634; SI-NEXT: v_mov_b32_e32 v0, s5635; SI-NEXT: v_mov_b32_e32 v1, s4636; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0637; SI-NEXT: s_endpgm638;639; VI-LABEL: scalar_xor_literal_i64:640; VI: ; %bb.0:641; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x4c642; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24643; VI-NEXT: s_waitcnt lgkmcnt(0)644; VI-NEXT: s_xor_b32 s1, s1, 0xf237b645; VI-NEXT: s_xor_b32 s0, s0, 0x3039646; VI-NEXT: v_mov_b32_e32 v2, s2647; VI-NEXT: v_mov_b32_e32 v0, s0648; VI-NEXT: v_mov_b32_e32 v1, s1649; VI-NEXT: v_mov_b32_e32 v3, s3650; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]651; VI-NEXT: s_endpgm652 %or = xor i64 %a, 4261135838621753653 store i64 %or, ptr addrspace(1) %out654 ret void655}656 657define amdgpu_kernel void @scalar_xor_literal_multi_use_i64(ptr addrspace(1) %out, [8 x i32], i64 %a, i64 %b) {658; SI-LABEL: scalar_xor_literal_multi_use_i64:659; SI: ; %bb.0:660; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9661; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x13662; SI-NEXT: s_movk_i32 s8, 0x3039663; SI-NEXT: s_mov_b32 s9, 0xf237b664; SI-NEXT: s_mov_b32 s3, 0xf000665; SI-NEXT: s_mov_b32 s2, -1666; SI-NEXT: s_waitcnt lgkmcnt(0)667; SI-NEXT: s_xor_b64 s[4:5], s[4:5], s[8:9]668; SI-NEXT: v_mov_b32_e32 v0, s4669; SI-NEXT: v_mov_b32_e32 v1, s5670; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0671; SI-NEXT: s_add_u32 s0, s6, 0x3039672; SI-NEXT: s_addc_u32 s1, s7, 0xf237b673; SI-NEXT: s_waitcnt expcnt(0)674; SI-NEXT: v_mov_b32_e32 v0, s0675; SI-NEXT: v_mov_b32_e32 v1, s1676; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0677; SI-NEXT: s_waitcnt vmcnt(0)678; SI-NEXT: s_endpgm679;680; VI-LABEL: scalar_xor_literal_multi_use_i64:681; VI: ; %bb.0:682; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x4c683; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24684; VI-NEXT: s_movk_i32 s6, 0x3039685; VI-NEXT: s_mov_b32 s7, 0xf237b686; VI-NEXT: s_waitcnt lgkmcnt(0)687; VI-NEXT: s_xor_b64 s[0:1], s[0:1], s[6:7]688; VI-NEXT: v_mov_b32_e32 v0, s4689; VI-NEXT: v_mov_b32_e32 v3, s1690; VI-NEXT: v_mov_b32_e32 v1, s5691; VI-NEXT: v_mov_b32_e32 v2, s0692; VI-NEXT: s_add_u32 s0, s2, 0x3039693; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]694; VI-NEXT: s_addc_u32 s1, s3, 0xf237b695; VI-NEXT: v_mov_b32_e32 v0, s0696; VI-NEXT: v_mov_b32_e32 v1, s1697; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]698; VI-NEXT: s_waitcnt vmcnt(0)699; VI-NEXT: s_endpgm700 %or = xor i64 %a, 4261135838621753701 store i64 %or, ptr addrspace(1) %out702 703 %foo = add i64 %b, 4261135838621753704 store volatile i64 %foo, ptr addrspace(1) poison705 ret void706}707 708define amdgpu_kernel void @scalar_xor_inline_imm_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {709; SI-LABEL: scalar_xor_inline_imm_i64:710; SI: ; %bb.0:711; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x13712; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9713; SI-NEXT: s_mov_b32 s3, 0xf000714; SI-NEXT: s_mov_b32 s2, -1715; SI-NEXT: s_waitcnt lgkmcnt(0)716; SI-NEXT: s_xor_b32 s4, s6, 63717; SI-NEXT: v_mov_b32_e32 v0, s4718; SI-NEXT: v_mov_b32_e32 v1, s7719; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0720; SI-NEXT: s_endpgm721;722; VI-LABEL: scalar_xor_inline_imm_i64:723; VI: ; %bb.0:724; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x4c725; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24726; VI-NEXT: s_waitcnt lgkmcnt(0)727; VI-NEXT: s_xor_b32 s0, s0, 63728; VI-NEXT: v_mov_b32_e32 v2, s2729; VI-NEXT: v_mov_b32_e32 v1, s1730; VI-NEXT: v_mov_b32_e32 v0, s0731; VI-NEXT: v_mov_b32_e32 v3, s3732; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]733; VI-NEXT: s_endpgm734 %or = xor i64 %a, 63735 store i64 %or, ptr addrspace(1) %out736 ret void737}738 739define amdgpu_kernel void @scalar_xor_neg_inline_imm_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {740; SI-LABEL: scalar_xor_neg_inline_imm_i64:741; SI: ; %bb.0:742; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x13743; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9744; SI-NEXT: s_mov_b32 s3, 0xf000745; SI-NEXT: s_mov_b32 s2, -1746; SI-NEXT: s_waitcnt lgkmcnt(0)747; SI-NEXT: s_xor_b64 s[4:5], s[6:7], -8748; SI-NEXT: v_mov_b32_e32 v0, s4749; SI-NEXT: v_mov_b32_e32 v1, s5750; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0751; SI-NEXT: s_endpgm752;753; VI-LABEL: scalar_xor_neg_inline_imm_i64:754; VI: ; %bb.0:755; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x4c756; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24757; VI-NEXT: s_waitcnt lgkmcnt(0)758; VI-NEXT: s_xor_b64 s[0:1], s[0:1], -8759; VI-NEXT: v_mov_b32_e32 v0, s2760; VI-NEXT: v_mov_b32_e32 v3, s1761; VI-NEXT: v_mov_b32_e32 v1, s3762; VI-NEXT: v_mov_b32_e32 v2, s0763; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]764; VI-NEXT: s_endpgm765 766 %or = xor i64 %a, -8767 store i64 %or, ptr addrspace(1) %out768 ret void769}770 771define amdgpu_kernel void @vector_xor_i64_neg_inline_imm(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {772; SI-LABEL: vector_xor_i64_neg_inline_imm:773; SI: ; %bb.0:774; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9775; SI-NEXT: s_mov_b32 s7, 0xf000776; SI-NEXT: s_mov_b32 s6, -1777; SI-NEXT: s_mov_b32 s10, s6778; SI-NEXT: s_mov_b32 s11, s7779; SI-NEXT: s_waitcnt lgkmcnt(0)780; SI-NEXT: s_mov_b32 s8, s2781; SI-NEXT: s_mov_b32 s9, s3782; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0783; SI-NEXT: s_mov_b32 s4, s0784; SI-NEXT: s_mov_b32 s5, s1785; SI-NEXT: s_waitcnt vmcnt(0)786; SI-NEXT: v_xor_b32_e32 v0, -8, v0787; SI-NEXT: v_xor_b32_e32 v1, -1, v1788; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0789; SI-NEXT: s_endpgm790;791; VI-LABEL: vector_xor_i64_neg_inline_imm:792; VI: ; %bb.0:793; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24794; VI-NEXT: s_waitcnt lgkmcnt(0)795; VI-NEXT: v_mov_b32_e32 v0, s2796; VI-NEXT: v_mov_b32_e32 v1, s3797; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]798; VI-NEXT: v_mov_b32_e32 v2, s0799; VI-NEXT: v_mov_b32_e32 v3, s1800; VI-NEXT: s_waitcnt vmcnt(0)801; VI-NEXT: v_xor_b32_e32 v0, -8, v0802; VI-NEXT: v_xor_b32_e32 v1, -1, v1803; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]804; VI-NEXT: s_endpgm805 %loada = load i64, ptr addrspace(1) %a, align 8806 %or = xor i64 %loada, -8807 store i64 %or, ptr addrspace(1) %out808 ret void809}810 811define amdgpu_kernel void @vector_xor_literal_i64(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {812; SI-LABEL: vector_xor_literal_i64:813; SI: ; %bb.0:814; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9815; SI-NEXT: s_mov_b32 s7, 0xf000816; SI-NEXT: s_mov_b32 s6, -1817; SI-NEXT: s_mov_b32 s10, s6818; SI-NEXT: s_mov_b32 s11, s7819; SI-NEXT: s_waitcnt lgkmcnt(0)820; SI-NEXT: s_mov_b32 s8, s2821; SI-NEXT: s_mov_b32 s9, s3822; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0823; SI-NEXT: s_mov_b32 s4, s0824; SI-NEXT: s_mov_b32 s5, s1825; SI-NEXT: s_waitcnt vmcnt(0)826; SI-NEXT: v_xor_b32_e32 v1, 0x146f, v1827; SI-NEXT: v_xor_b32_e32 v0, 0xdf77987f, v0828; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0829; SI-NEXT: s_endpgm830;831; VI-LABEL: vector_xor_literal_i64:832; VI: ; %bb.0:833; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24834; VI-NEXT: s_waitcnt lgkmcnt(0)835; VI-NEXT: v_mov_b32_e32 v0, s2836; VI-NEXT: v_mov_b32_e32 v1, s3837; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]838; VI-NEXT: v_mov_b32_e32 v2, s0839; VI-NEXT: v_mov_b32_e32 v3, s1840; VI-NEXT: s_waitcnt vmcnt(0)841; VI-NEXT: v_xor_b32_e32 v1, 0x146f, v1842; VI-NEXT: v_xor_b32_e32 v0, 0xdf77987f, v0843; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]844; VI-NEXT: s_endpgm845 846 %loada = load i64, ptr addrspace(1) %a, align 8847 %or = xor i64 %loada, 22470723082367848 store i64 %or, ptr addrspace(1) %out849 ret void850}851