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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 | FileCheck -check-prefix=GFX9 %s3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 | FileCheck -check-prefix=GFX10 %s4; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s5 6; ===================================================================================7; V_XOR3_B328; ===================================================================================9 10define amdgpu_ps float @xor3(i32 %a, i32 %b, i32 %c) {11; GFX9-LABEL: xor3:12; GFX9: ; %bb.0:13; GFX9-NEXT: v_xor_b32_e32 v0, v0, v114; GFX9-NEXT: v_xor_b32_e32 v0, v0, v215; GFX9-NEXT: ; return to shader part epilog16;17; GFX10-LABEL: xor3:18; GFX10: ; %bb.0:19; GFX10-NEXT: v_xor3_b32 v0, v0, v1, v220; GFX10-NEXT: ; return to shader part epilog21 %x = xor i32 %a, %b22 %result = xor i32 %x, %c23 %bc = bitcast i32 %result to float24 ret float %bc25}26 27define amdgpu_ps float @xor3_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {28; GFX9-LABEL: xor3_vgpr_b:29; GFX9: ; %bb.0:30; GFX9-NEXT: s_xor_b32 s0, s3, s231; GFX9-NEXT: v_xor_b32_e32 v0, s0, v032; GFX9-NEXT: ; return to shader part epilog33;34; GFX10-LABEL: xor3_vgpr_b:35; GFX10: ; %bb.0:36; GFX10-NEXT: v_xor3_b32 v0, s3, s2, v037; GFX10-NEXT: ; return to shader part epilog38 %x = xor i32 %a, %b39 %result = xor i32 %x, %c40 %bc = bitcast i32 %result to float41 ret float %bc42}43 44define amdgpu_ps float @xor3_vgpr_all2(i32 %a, i32 %b, i32 %c) {45; GFX9-LABEL: xor3_vgpr_all2:46; GFX9: ; %bb.0:47; GFX9-NEXT: v_xor_b32_e32 v1, v1, v248; GFX9-NEXT: v_xor_b32_e32 v0, v0, v149; GFX9-NEXT: ; return to shader part epilog50;51; GFX10-LABEL: xor3_vgpr_all2:52; GFX10: ; %bb.0:53; GFX10-NEXT: v_xor3_b32 v0, v1, v2, v054; GFX10-NEXT: ; return to shader part epilog55 %x = xor i32 %b, %c56 %result = xor i32 %a, %x57 %bc = bitcast i32 %result to float58 ret float %bc59}60 61define amdgpu_ps float @xor3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {62; GFX9-LABEL: xor3_vgpr_bc:63; GFX9: ; %bb.0:64; GFX9-NEXT: v_xor_b32_e32 v0, s2, v065; GFX9-NEXT: v_xor_b32_e32 v0, v0, v166; GFX9-NEXT: ; return to shader part epilog67;68; GFX10-LABEL: xor3_vgpr_bc:69; GFX10: ; %bb.0:70; GFX10-NEXT: v_xor3_b32 v0, s2, v0, v171; GFX10-NEXT: ; return to shader part epilog72 %x = xor i32 %a, %b73 %result = xor i32 %x, %c74 %bc = bitcast i32 %result to float75 ret float %bc76}77 78define amdgpu_ps float @xor3_vgpr_const(i32 %a, i32 %b) {79; GFX9-LABEL: xor3_vgpr_const:80; GFX9: ; %bb.0:81; GFX9-NEXT: v_xor_b32_e32 v0, v0, v182; GFX9-NEXT: v_xor_b32_e32 v0, 16, v083; GFX9-NEXT: ; return to shader part epilog84;85; GFX10-LABEL: xor3_vgpr_const:86; GFX10: ; %bb.0:87; GFX10-NEXT: v_xor3_b32 v0, v0, v1, 1688; GFX10-NEXT: ; return to shader part epilog89 %x = xor i32 %a, %b90 %result = xor i32 %x, 1691 %bc = bitcast i32 %result to float92 ret float %bc93}94 95define amdgpu_ps <2 x float> @xor3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x) {96; GFX9-LABEL: xor3_multiuse_outer:97; GFX9: ; %bb.0:98; GFX9-NEXT: v_xor_b32_e32 v0, v0, v199; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2100; GFX9-NEXT: v_mul_lo_u32 v1, v0, v3101; GFX9-NEXT: ; return to shader part epilog102;103; GFX10-LABEL: xor3_multiuse_outer:104; GFX10: ; %bb.0:105; GFX10-NEXT: v_xor3_b32 v0, v0, v1, v2106; GFX10-NEXT: v_mul_lo_u32 v1, v0, v3107; GFX10-NEXT: ; return to shader part epilog108 %inner = xor i32 %a, %b109 %outer = xor i32 %inner, %c110 %x1 = mul i32 %outer, %x111 %r1 = insertelement <2 x i32> poison, i32 %outer, i32 0112 %r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1113 %bc = bitcast <2 x i32> %r0 to <2 x float>114 ret <2 x float> %bc115}116 117define amdgpu_ps <2 x float> @xor3_multiuse_inner(i32 %a, i32 %b, i32 %c) {118; GFX9-LABEL: xor3_multiuse_inner:119; GFX9: ; %bb.0:120; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1121; GFX9-NEXT: v_xor_b32_e32 v1, v0, v2122; GFX9-NEXT: ; return to shader part epilog123;124; GFX10-LABEL: xor3_multiuse_inner:125; GFX10: ; %bb.0:126; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1127; GFX10-NEXT: v_xor_b32_e32 v1, v0, v2128; GFX10-NEXT: ; return to shader part epilog129 %inner = xor i32 %a, %b130 %outer = xor i32 %inner, %c131 %r1 = insertelement <2 x i32> poison, i32 %inner, i32 0132 %r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1133 %bc = bitcast <2 x i32> %r0 to <2 x float>134 ret <2 x float> %bc135}136 137; A case where uniform values end up in VGPRs -- we could use v_xor3_b32 here,138; but we don't.139define amdgpu_ps float @xor3_uniform_vgpr(float inreg %a, float inreg %b, float inreg %c) {140; GFX9-LABEL: xor3_uniform_vgpr:141; GFX9: ; %bb.0:142; GFX9-NEXT: v_add_f32_e64 v0, s2, 1.0143; GFX9-NEXT: v_add_f32_e64 v1, s3, 2.0144; GFX9-NEXT: v_mov_b32_e32 v2, 0x40400000145; GFX9-NEXT: v_add_f32_e32 v2, s4, v2146; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1147; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2148; GFX9-NEXT: ; return to shader part epilog149;150; GFX10-LABEL: xor3_uniform_vgpr:151; GFX10: ; %bb.0:152; GFX10-NEXT: v_add_f32_e64 v0, s2, 1.0153; GFX10-NEXT: v_add_f32_e64 v1, s3, 2.0154; GFX10-NEXT: v_add_f32_e64 v2, 0x40400000, s4155; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1156; GFX10-NEXT: v_xor_b32_e32 v0, v0, v2157; GFX10-NEXT: ; return to shader part epilog158 %a1 = fadd float %a, 1.0159 %b2 = fadd float %b, 2.0160 %c3 = fadd float %c, 3.0161 %bc.a = bitcast float %a1 to i32162 %bc.b = bitcast float %b2 to i32163 %bc.c = bitcast float %c3 to i32164 %x = xor i32 %bc.a, %bc.b165 %result = xor i32 %x, %bc.c166 %bc = bitcast i32 %result to float167 ret float %bc168}169