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1; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s2 3; GCN-LABEL: {{^}}zext_or_operand_i64:4; GCN: buffer_load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]5; GCN: buffer_load_dword v[[LD32:[0-9]+]]6; GCN-NOT: _or_7; GCN-NOT: v[[HI]]8; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 09; GCN: v_or_b32_e32 v[[LO]], v[[LO]], v[[LD32]]10; GCN-NOT: _or_11; GCN-NOT: v[[HI]]12; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 013; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]14define amdgpu_kernel void @zext_or_operand_i64(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {15 %ld.64 = load volatile i64, ptr addrspace(1) %in016 %ld.32 = load volatile i32, ptr addrspace(1) %in117 %ext = zext i32 %ld.32 to i6418 %or = or i64 %ld.64, %ext19 store i64 %or, ptr addrspace(1) %out20 ret void21}22 23; GCN-LABEL: {{^}}zext_or_operand_commute_i64:24; GCN: buffer_load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]25; GCN: buffer_load_dword v[[LD32:[0-9]+]]26; GCN-NOT: _or_27; GCN-NOT: v[[HI]]28; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 029; GCN: v_or_b32_e32 v[[LO]], v[[LO]], v[[LD32]]30; GCN-NOT: v[[HI]]31; GCN-NOT: _or_32; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 033; GCN: buffer_store_dwordx2 v[[[LO]]:[[HI]]]34define amdgpu_kernel void @zext_or_operand_commute_i64(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {35 %ld.64 = load volatile i64, ptr addrspace(1) %in036 %ld.32 = load volatile i32, ptr addrspace(1) %in137 %ext = zext i32 %ld.32 to i6438 %or = or i64 %ext, %ld.6439 store i64 %or, ptr addrspace(1) %out40 ret void41}42