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1; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=GCN,O2 %s2; RUN: llc -O0 -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCN %s3 4; GCN-LABEL: {{^}}zext_grp_size_128:5; GCN-NOT: and_b326define amdgpu_kernel void @zext_grp_size_128(ptr addrspace(1) nocapture %arg) #0 {7bb:8 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()9 %tmp1 = and i32 %tmp, 12710 store i32 %tmp1, ptr addrspace(1) %arg, align 411 %tmp2 = tail call i32 @llvm.amdgcn.workitem.id.y()12 %tmp3 = and i32 %tmp2, 12713 %tmp4 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 114 store i32 %tmp3, ptr addrspace(1) %tmp4, align 415 %tmp5 = tail call i32 @llvm.amdgcn.workitem.id.z()16 %tmp6 = and i32 %tmp5, 12717 %tmp7 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 218 store i32 %tmp6, ptr addrspace(1) %tmp7, align 419 ret void20}21 22; GCN-LABEL: {{^}}zext_grp_size_32x4x1:23; GCN-NOT: and_b3224define amdgpu_kernel void @zext_grp_size_32x4x1(ptr addrspace(1) nocapture %arg) #0 !reqd_work_group_size !0 {25bb:26 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()27 %tmp1 = and i32 %tmp, 3128 store i32 %tmp1, ptr addrspace(1) %arg, align 429 %tmp2 = tail call i32 @llvm.amdgcn.workitem.id.y()30 %tmp3 = and i32 %tmp2, 331 %tmp4 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 132 store i32 %tmp3, ptr addrspace(1) %tmp4, align 433 %tmp5 = tail call i32 @llvm.amdgcn.workitem.id.z()34 %tmp6 = and i32 %tmp5, 135 %tmp7 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 236 store i32 %tmp6, ptr addrspace(1) %tmp7, align 437 ret void38}39 40; GCN-LABEL: {{^}}zext_grp_size_1x1x1:41; GCN-NOT: and_b3242 43; When EarlyCSE is not run this call produces a range max with 0 active bits,44; which is a special case as an AssertZext from width 0 is invalid.45define amdgpu_kernel void @zext_grp_size_1x1x1(ptr addrspace(1) nocapture %arg) #0 !reqd_work_group_size !1 {46 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()47 %tmp1 = and i32 %tmp, 148 store i32 %tmp1, ptr addrspace(1) %arg, align 449 ret void50}51 52; GCN-LABEL: {{^}}zext_grp_size_512:53; GCN-NOT: and_b3254define amdgpu_kernel void @zext_grp_size_512(ptr addrspace(1) nocapture %arg) #1 {55bb:56 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()57 %tmp1 = and i32 %tmp, 6553558 store i32 %tmp1, ptr addrspace(1) %arg, align 459 %tmp2 = tail call i32 @llvm.amdgcn.workitem.id.y()60 %tmp3 = and i32 %tmp2, 6553561 %tmp4 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 162 store i32 %tmp3, ptr addrspace(1) %tmp4, align 463 %tmp5 = tail call i32 @llvm.amdgcn.workitem.id.z()64 %tmp6 = and i32 %tmp5, 6553565 %tmp7 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 266 store i32 %tmp6, ptr addrspace(1) %tmp7, align 467 ret void68}69 70; GCN-LABEL: {{^}}func_test_workitem_id_x_known_max_range:71; O2-NOT: and_b3272; O2: v_and_b32_e32 v{{[0-9]+}}, 0x3ff,73; O2-NOT: and_b3274define void @func_test_workitem_id_x_known_max_range(ptr addrspace(1) nocapture %out) #0 {75entry:76 %id = tail call i32 @llvm.amdgcn.workitem.id.x()77 %and = and i32 %id, 102378 store i32 %and, ptr addrspace(1) %out, align 479 ret void80}81 82; GCN-LABEL: {{^}}func_test_workitem_id_x_default_range:83; O2-NOT: and_b3284; O2: v_and_b32_e32 v{{[0-9]+}}, 0x3ff,85; O2-NOT: and_b3286define void @func_test_workitem_id_x_default_range(ptr addrspace(1) nocapture %out) #4 {87entry:88 %id = tail call i32 @llvm.amdgcn.workitem.id.x()89 %and = and i32 %id, 102390 store i32 %and, ptr addrspace(1) %out, align 491 ret void92}93 94declare i32 @llvm.amdgcn.workitem.id.x() #295 96declare i32 @llvm.amdgcn.workitem.id.y() #297 98declare i32 @llvm.amdgcn.workitem.id.z() #299 100attributes #0 = { nounwind "amdgpu-flat-work-group-size"="64,128" }101attributes #1 = { nounwind "amdgpu-flat-work-group-size"="512,512" }102attributes #2 = { nounwind readnone speculatable }103attributes #3 = { nounwind readnone }104attributes #4 = { nounwind }105 106!0 = !{i32 32, i32 4, i32 1}107!1 = !{i32 1, i32 1, i32 1}108