273 lines · plain
1; RUN: llc -mtriple=arc < %s | FileCheck %s2 3; CHECK-LABEL: add_r4; CHECK: add %r0, %r{{[01]}}, %r{{[01]}}5define i32 @add_r(i32 %a, i32 %b) nounwind {6entry:7 %v = add i32 %a, %b8 ret i32 %v9}10 11; CHECK-LABEL: add_u612; CHECK: add %r0, %r0, 1513define i32 @add_u6(i32 %a) nounwind {14 %v = add i32 %a, 1515 ret i32 %v16}17 18; CHECK-LABEL: add_limm19; CHECK: add %r0, %r0, 1234520define i32 @add_limm(i32 %a) nounwind {21 %v = add i32 %a, 1234522 ret i32 %v23}24 25; CHECK-LABEL: mpy_r26; CHECK: mpy %r0, %r{{[01]}}, %r{{[01]}}27define i32 @mpy_r(i32 %a, i32 %b) nounwind {28entry:29 %v = mul i32 %a, %b30 ret i32 %v31}32 33; CHECK-LABEL: mpy_u634; CHECK: mpy %r0, %r0, 1035define i32 @mpy_u6(i32 %a) nounwind {36 %v = mul i32 %a, 1037 ret i32 %v38}39 40; CHECK-LABEL: mpy_limm41; CHECK: mpy %r0, %r0, 1234542define i32 @mpy_limm(i32 %a) nounwind {43 %v = mul i32 %a, 1234544 ret i32 %v45}46 47; CHECK-LABEL: max_r48; CHECK: max %r0, %r{{[01]}}, %r{{[01]}}49define i32 @max_r(i32 %a, i32 %b) nounwind {50 %i = icmp sgt i32 %a, %b51 %v = select i1 %i, i32 %a, i32 %b52 ret i32 %v53}54 55; CHECK-LABEL: max_u656; CHECK: max %r0, %r0, 1257define i32 @max_u6(i32 %a) nounwind {58 %i = icmp sgt i32 %a, 1259 %v = select i1 %i, i32 %a, i32 1260 ret i32 %v61}62 63; CHECK-LABEL: max_limm64; CHECK: max %r0, %r0, 234565define i32 @max_limm(i32 %a) nounwind {66 %i = icmp sgt i32 %a, 234567 %v = select i1 %i, i32 %a, i32 234568 ret i32 %v69}70 71; CHECK-LABEL: min_r72; CHECK: min %r0, %r{{[01]}}, %r{{[01]}}73define i32 @min_r(i32 %a, i32 %b) nounwind {74 %i = icmp slt i32 %a, %b75 %v = select i1 %i, i32 %a, i32 %b76 ret i32 %v77}78 79; CHECK-LABEL: min_u680; CHECK: min %r0, %r0, 2081define i32 @min_u6(i32 %a) nounwind {82 %i = icmp slt i32 %a, 2083 %v = select i1 %i, i32 %a, i32 2084 ret i32 %v85}86 87; CHECK-LABEL: min_limm88; CHECK: min %r0, %r0, 204089define i32 @min_limm(i32 %a) nounwind {90 %i = icmp slt i32 %a, 204091 %v = select i1 %i, i32 %a, i32 204092 ret i32 %v93}94 95; CHECK-LABEL: and_r96; CHECK: and %r0, %r{{[01]}}, %r{{[01]}}97define i32 @and_r(i32 %a, i32 %b) nounwind {98 %v = and i32 %a, %b99 ret i32 %v100}101 102; CHECK-LABEL: and_u6103; CHECK: and %r0, %r0, 7104define i32 @and_u6(i32 %a) nounwind {105 %v = and i32 %a, 7106 ret i32 %v107}108 109; 0xfffff == 1048575110; CHECK-LABEL: and_limm111; CHECK: and %r0, %r0, 1048575 112define i32 @and_limm(i32 %a) nounwind {113 %v = and i32 %a, 1048575114 ret i32 %v115}116 117; CHECK-LABEL: or_r118; CHECK: or %r0, %r{{[01]}}, %r{{[01]}}119define i32 @or_r(i32 %a, i32 %b) nounwind {120 %v = or i32 %a, %b121 ret i32 %v122}123 124; CHECK-LABEL: or_u6125; CHECK: or %r0, %r0, 7126define i32 @or_u6(i32 %a) nounwind {127 %v = or i32 %a, 7128 ret i32 %v129}130 131; 0xf0f0f == 986895132; CHECK-LABEL: or_limm133define i32 @or_limm(i32 %a) nounwind {134 %v = or i32 %a, 986895135 ret i32 %v136}137 138; CHECK-LABEL: xor_r139; CHECK: xor %r0, %r{{[01]}}, %r{{[01]}}140define i32 @xor_r(i32 %a, i32 %b) nounwind {141 %v = xor i32 %a, %b142 ret i32 %v143}144 145; CHECK-LABEL: xor_u6146; CHECK: xor %r0, %r0, 3147define i32 @xor_u6(i32 %a) nounwind {148 %v = xor i32 %a, 3149 ret i32 %v150}151 152; CHECK-LABEL: xor_limm153; CHECK: xor %r0, %r0, 986895154define i32 @xor_limm(i32 %a) nounwind {155 %v = xor i32 %a, 986895156 ret i32 %v157}158 159; CHECK-LABEL: asl_r160; CHECK: asl %r0, %r{{[01]}}, %r{{[01]}}161define i32 @asl_r(i32 %a, i32 %b) nounwind {162 %v = shl i32 %a, %b163 ret i32 %v164}165 166; CHECK-LABEL: asl_u6167; CHECK: asl %r0, %r0, 4168define i32 @asl_u6(i32 %a) nounwind {169 %v = shl i32 %a, 4170 ret i32 %v171}172 173; CHECK-LABEL: lsr_r174; CHECK: lsr %r0, %r{{[01]}}, %r{{[01]}}175define i32 @lsr_r(i32 %a, i32 %b) nounwind {176 %v = lshr i32 %a, %b177 ret i32 %v178}179 180; CHECK-LABEL: lsr_u6181; CHECK: lsr %r0, %r0, 6182define i32 @lsr_u6(i32 %a) nounwind {183 %v = lshr i32 %a, 6184 ret i32 %v185}186 187; CHECK-LABEL: asr_r188; CHECK: asr %r0, %r{{[01]}}, %r{{[01]}}189define i32 @asr_r(i32 %a, i32 %b) nounwind {190 %v = ashr i32 %a, %b191 ret i32 %v192}193 194; CHECK-LABEL: asr_u6195; CHECK: asr %r0, %r0, 8196define i32 @asr_u6(i32 %a) nounwind {197 %v = ashr i32 %a, 8198 ret i32 %v199}200 201; CHECK-LABEL: ror_r202; CHECK: ror %r0, %r{{[01]}}, %r{{[01]}}203define i32 @ror_r(i32 %a, i32 %b) nounwind {204 %v1 = lshr i32 %a, %b205 %ls = sub i32 32, %b206 %v2 = shl i32 %a, %ls207 %v = or i32 %v1, %v2208 ret i32 %v209}210 211; CHECK-LABEL: ror_u6212; CHECK: ror %r0, %r0, 10213define i32 @ror_u6(i32 %a) nounwind {214 %v1 = lshr i32 %a, 10215 %v2 = shl i32 %a, 22216 %v = or i32 %v1, %v2217 ret i32 %v218}219 220; CHECK-LABEL: sexh_r221; CHECK: sexh %r0, %r0222define i32 @sexh_r(i32 %a) nounwind {223 %v1 = shl i32 %a, 16224 %v = ashr i32 %v1, 16225 ret i32 %v226}227 228; CHECK-LABEL: sexb_r229; CHECK: sexb %r0, %r0230define i32 @sexb_r(i32 %a) nounwind {231 %v1 = shl i32 %a, 24232 %v = ashr i32 %v1, 24233 ret i32 %v234}235 236; CHECK-LABEL: mulu64237; CHECK-DAG: mpy %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}238; CHECK-DAG: mpymu %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}239define i64 @mulu64(i32 %a, i32 %b) nounwind {240 %a64 = zext i32 %a to i64241 %b64 = zext i32 %b to i64242 %v = mul i64 %a64, %b64243 ret i64 %v244}245 246; CHECK-LABEL: muls64247; CHECK-DAG: mpy %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}248; CHECK-DAG: mpym %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}249define i64 @muls64(i32 %a, i32 %b) nounwind {250 %a64 = sext i32 %a to i64251 %b64 = sext i32 %b to i64252 %v = mul i64 %a64, %b64253 ret i64 %v254}255 256; CHECK-LABEL: long_long_add257; CHECK: add.f %r0, %r0, %r2258; CHECK-NEXT: adc.f %r1, %r1, %r3259define i64 @long_long_add(i64 inreg %a, i64 inreg %b) #0 {260entry:261 %add = add nsw i64 %a, %b262 ret i64 %add263}264 265; CHECK-LABEL: long_long_sub266; CHECK: sub.f %r0, %r0, %r2267; CHECK-NEXT: sbc.f %r1, %r1, %r3268define i64 @long_long_sub(i64 inreg %a, i64 inreg %b) #0 {269entry:270 %sub = sub nsw i64 %a, %b271 ret i64 %sub272}273