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1; RUN: llc -mattr=+neon < %s2; PR49653target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"4target triple = "armv7-eabi"5 6%struct.fr = type { [6 x %struct.pl] }7%struct.obb = type { %"struct.m4", %"struct.p3" }8%struct.pl = type { %"struct.p3" }9%"struct.m4" = type { %"struct.p3", %"struct.p3", %"struct.p3", %"struct.p3" }10%"struct.p3" = type { <4 x float> }11 12declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone13 14define arm_aapcs_vfpcc i8 @foo(ptr nocapture %this, ptr %box) nounwind {15entry:16 %val.i.i = load <4 x float>, ptr undef ; <<4 x float>> [#uses=1]17 %val2.i.i = load <4 x float>, ptr null ; <<4 x float>> [#uses=1]18 %elt3.i.i = getelementptr inbounds %struct.obb, ptr %box, i32 0, i32 0, i32 2, i32 0 ; <ptr> [#uses=1]19 %val4.i.i = load <4 x float>, ptr %elt3.i.i ; <<4 x float>> [#uses=1]20 %0 = shufflevector <2 x float> undef, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]21 %1 = fadd <4 x float> undef, zeroinitializer ; <<4 x float>> [#uses=1]22 br label %bb3323 24bb: ; preds = %bb3325 %2 = fmul <4 x float> %val.i.i, undef ; <<4 x float>> [#uses=1]26 %3 = fmul <4 x float> %val2.i.i, undef ; <<4 x float>> [#uses=1]27 %4 = fadd <4 x float> %3, %2 ; <<4 x float>> [#uses=1]28 %5 = fmul <4 x float> %val4.i.i, undef ; <<4 x float>> [#uses=1]29 %6 = fadd <4 x float> %5, %4 ; <<4 x float>> [#uses=1]30 %7 = bitcast <4 x float> %6 to <4 x i32> ; <<4 x i32>> [#uses=1]31 %8 = and <4 x i32> %7, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> ; <<4 x i32>> [#uses=1]32 %9 = or <4 x i32> %8, undef ; <<4 x i32>> [#uses=1]33 %10 = bitcast <4 x i32> %9 to <4 x float> ; <<4 x float>> [#uses=1]34 %11 = shufflevector <4 x float> %10, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]35 %12 = shufflevector <2 x float> %11, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]36 %13 = fmul <4 x float> undef, %12 ; <<4 x float>> [#uses=1]37 %14 = fmul <4 x float> %0, undef ; <<4 x float>> [#uses=1]38 %15 = fadd <4 x float> %14, %13 ; <<4 x float>> [#uses=1]39 %16 = fadd <4 x float> undef, %15 ; <<4 x float>> [#uses=1]40 %17 = fadd <4 x float> %1, %16 ; <<4 x float>> [#uses=1]41 %18 = fmul <4 x float> zeroinitializer, %17 ; <<4 x float>> [#uses=1]42 %19 = insertelement <4 x float> %18, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=2]43 %20 = shufflevector <4 x float> %19, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]44 %21 = shufflevector <4 x float> %19, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]45 %22 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %20, <2 x float> %21) nounwind ; <<2 x float>> [#uses=2]46 %23 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %22, <2 x float> %22) nounwind ; <<2 x float>> [#uses=2]47 %24 = shufflevector <2 x float> %23, <2 x float> %23, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]48 %25 = fadd <4 x float> %24, zeroinitializer ; <<4 x float>> [#uses=1]49 %tmp46 = extractelement <4 x float> %25, i32 0 ; <float> [#uses=1]50 %26 = fcmp olt float %tmp46, 0.000000e+00 ; <i1> [#uses=1]51 br i1 %26, label %bb41, label %bb3352 53bb33: ; preds = %bb, %entry54 br i1 undef, label %bb34, label %bb55 56bb34: ; preds = %bb3357 ret i8 undef58 59bb41: ; preds = %bb60 ret i8 161}62