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1; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a82; PR50553 4module asm ".globl\09__aeabi_f2lz"5module asm ".set\09__aeabi_f2lz, __fixsfdi"6module asm ""7 8define arm_aapcs_vfpcc i64 @__fixsfdi(float %a) nounwind {9entry:10 %0 = fcmp olt float %a, 0.000000e+00 ; <i1> [#uses=1]11 br i1 %0, label %bb, label %bb112 13bb: ; preds = %entry14 %1 = fsub float -0.000000e+00, %a ; <float> [#uses=1]15 %2 = tail call arm_aapcs_vfpcc i64 @__fixunssfdi(float %1) nounwind ; <i64> [#uses=1]16 %3 = sub i64 0, %2 ; <i64> [#uses=1]17 ret i64 %318 19bb1: ; preds = %entry20 %4 = tail call arm_aapcs_vfpcc i64 @__fixunssfdi(float %a) nounwind ; <i64> [#uses=1]21 ret i64 %422}23 24declare arm_aapcs_vfpcc i64 @__fixunssfdi(float)25