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1; RUN: llc < %s -O0 -mcpu=cortex-a8 | FileCheck %s2target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"3target triple = "thumbv7-apple-darwin10"4 5; This tests the fast register allocator's handling of partial redefines:6;7; %reg1028:dsub_0, %reg1028:dsub_1 = VLD1q64 %reg1025...8; %reg1030:dsub_1 = COPY killed %reg1028:dsub_09;10; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial11; redef, it cannot also get %Q0.12 13; CHECK: vld1.64 {d16, d17}, [r{{.}}]14; CHECK-NOT: vld1.64 {d16, d17}15; CHECK: vmov.f6416 17define i32 @test(ptr %arg) nounwind {18entry:19 %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0(ptr %arg, i32 1)20 %1 = shufflevector <2 x i64> undef, <2 x i64> %0, <2 x i32> <i32 1, i32 2>21 store <2 x i64> %1, ptr undef, align 1622 ret i32 undef23}24 25declare <2 x i64> @llvm.arm.neon.vld1.v2i64.p0(ptr, i32) nounwind readonly26