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1; RUN: llc < %s -verify-machineinstrs2; PR86123;4; This test has an inline asm with early-clobber arguments.5; It is big enough that one of the early clobber registers is spilled.6;7; All the spillers would get the live ranges wrong when spilling an early8; clobber, allowing the undef register to be allocated to the same register as9; the early clobber.10;11target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32"12target triple = "armv7-eabi"13 14%0 = type { i32, i32 }15 16define void @foo(ptr %in) nounwind {17entry:18 br label %bb.i19 20bb.i: ; preds = %bb.i, %entry21 br i1 undef, label %bb10.preheader.i, label %bb.i22 23bb10.preheader.i: ; preds = %bb.i24 br label %bb10.i25 26bb10.i: ; preds = %bb10.i, %bb10.preheader.i27 br i1 undef, label %bb27.i, label %bb10.i28 29bb27.i: ; preds = %bb10.i30 br label %bb28.i31 32bb28.i: ; preds = %bb28.i, %bb27.i33 br i1 undef, label %presymmetry.exit, label %bb28.i34 35presymmetry.exit: ; preds = %bb28.i36 %tmp175387 = or i32 undef, 1237 %scevgep101.i = getelementptr i32, ptr %in, i32 undef38 %tmp189401 = or i32 undef, 739 %scevgep97.i = getelementptr i32, ptr %in, i32 undef40 %tmp198410 = or i32 undef, 141 %scevgep.i48 = getelementptr i32, ptr %in, i32 undef42 %0 = load i32, ptr %scevgep.i48, align 443 %1 = add nsw i32 %0, 044 store i32 %1, ptr undef, align 445 %asmtmp.i.i33.i.i.i = tail call %0 asm "smull\09$0, $1, $2, $3", "=&r,=&r,%r,r,~{cc}"(i32 undef, i32 1518500250) nounwind46 %asmresult1.i.i34.i.i.i = extractvalue %0 %asmtmp.i.i33.i.i.i, 147 %2 = shl i32 %asmresult1.i.i34.i.i.i, 148 %3 = load i32, ptr null, align 449 %4 = load i32, ptr undef, align 450 %5 = sub nsw i32 %3, %451 %6 = load i32, ptr undef, align 452 %7 = load i32, ptr null, align 453 %8 = sub nsw i32 %6, %754 %9 = load i32, ptr %scevgep97.i, align 455 %10 = load i32, ptr undef, align 456 %11 = sub nsw i32 %9, %1057 %12 = load i32, ptr null, align 458 %13 = load i32, ptr %scevgep101.i, align 459 %14 = sub nsw i32 %12, %1360 %15 = load i32, ptr %scevgep.i48, align 461 %16 = load i32, ptr null, align 462 %17 = add nsw i32 %16, %1563 %18 = sub nsw i32 %15, %1664 %19 = load i32, ptr undef, align 465 %20 = add nsw i32 %19, %266 %21 = sub nsw i32 %19, %267 %22 = add nsw i32 %14, %568 %23 = sub nsw i32 %5, %1469 %24 = add nsw i32 %11, %870 %25 = sub nsw i32 %8, %1171 %26 = add nsw i32 %21, %2372 store i32 %26, ptr %scevgep.i48, align 473 %27 = sub nsw i32 %25, %1874 store i32 %27, ptr null, align 475 %28 = sub nsw i32 %23, %2176 store i32 %28, ptr undef, align 477 %29 = add nsw i32 %18, %2578 store i32 %29, ptr undef, align 479 %30 = add nsw i32 %17, %2280 store i32 %30, ptr %scevgep101.i, align 481 %31 = add nsw i32 %20, %2482 store i32 %31, ptr null, align 483 unreachable84}85