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1; RUN: llc < %s -asm-verbose=false -O3 -mtriple=armv6-apple-darwin -relocation-model=pic -mcpu=arm1136jf-s -arm-atomic-cfg-tidy=0 | FileCheck %s2; rdar://8959122 illegal register operands for UMULL instruction3; in cfrac nightly test.4; Armv6 generates a umull that must write to two distinct destination regs.5 6; ModuleID = 'bugpoint-reduced-simplified.bc'7target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32"8target triple = "armv6-apple-darwin10"9 10define void @ptoa(i1 %tst, ptr %p8, i8 %val8) nounwind {11entry:12 br i1 false, label %bb3, label %bb13 14bb: ; preds = %entry15 br label %bb316 17bb3: ; preds = %bb, %entry18 %0 = call noalias ptr @malloc() nounwind19 br i1 %tst, label %bb46, label %bb820 21bb8: ; preds = %bb322 store volatile i8 0, ptr %0, align 123 %1 = call i32 @ptou() nounwind24 ; CHECK: umull [[REGISTER:lr|r[0-9]+]],25 ; CHECK-NOT: [[REGISTER]],26 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}27 ; CHECK: umull [[REGISTER:lr|r[0-9]+]],28 ; CHECK-NOT: [[REGISTER]],29 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}30 %2 = udiv i32 %1, 1031 %3 = urem i32 %2, 1032 %4 = icmp ult i32 %3, 1033 %5 = trunc i32 %3 to i834 %6 = or i8 %5, 4835 %7 = add i8 %5, 8736 %iftmp.5.0.1 = select i1 %4, i8 %6, i8 %737 store volatile i8 %iftmp.5.0.1, ptr %p8, align 138 ; CHECK: umull [[REGISTER:lr|r[0-9]+]],39 ; CHECK-NOT: [[REGISTER]],40 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}41 ; CHECK: umull [[REGISTER:lr|r[0-9]+]],42 ; CHECK-NOT: [[REGISTER]],43 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}44 %8 = udiv i32 %1, 10045 %9 = urem i32 %8, 1046 %10 = icmp ult i32 %9, 1047 %11 = trunc i32 %9 to i848 %12 = or i8 %11, 4849 %13 = add i8 %11, 8750 %iftmp.5.0.2 = select i1 %10, i8 %12, i8 %1351 store volatile i8 %iftmp.5.0.2, ptr %p8, align 152 ; CHECK: umull [[REGISTER:lr|r[0-9]+]],53 ; CHECK-NOT: [[REGISTER]],54 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}55 ; CHECK: umull [[REGISTER:lr|r[0-9]+]],56 ; CHECK-NOT: [[REGISTER]],57 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}58 %14 = udiv i32 %1, 1000059 %15 = urem i32 %14, 1060 %16 = icmp ult i32 %15, 1061 %17 = trunc i32 %15 to i862 %18 = or i8 %17, 4863 %19 = add i8 %17, 8764 %iftmp.5.0.4 = select i1 %16, i8 %18, i8 %1965 store volatile i8 %iftmp.5.0.4, ptr null, align 166 ; CHECK: umull [[REGISTER:lr|r[0-9]+]],67 ; CHECK-NOT: [[REGISTER]],68 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}69 ; CHECK: umull [[REGISTER:lr|r[0-9]+]],70 ; CHECK-NOT: [[REGISTER]],71 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}72 %20 = udiv i32 %1, 10000073 %21 = urem i32 %20, 1074 %22 = icmp ult i32 %21, 1075 %iftmp.5.0.5 = select i1 %22, i8 0, i8 %val876 store volatile i8 %iftmp.5.0.5, ptr %p8, align 177 ; CHECK: umull [[REGISTER:lr|r[0-9]+]],78 ; CHECK-NOT: [[REGISTER]],79 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}80 ; CHECK: umull [[REGISTER:lr|r[0-9]+]],81 ; CHECK-NOT: [[REGISTER]],82 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}83 %23 = udiv i32 %1, 100000084 %24 = urem i32 %23, 1085 %25 = icmp ult i32 %24, 1086 %26 = trunc i32 %24 to i887 %27 = or i8 %26, 4888 %28 = add i8 %26, 8789 %iftmp.5.0.6 = select i1 %25, i8 %27, i8 %2890 store volatile i8 %iftmp.5.0.6, ptr %p8, align 191 ; CHECK: umull [[REGISTER:lr|r[0-9]+]],92 ; CHECK-NOT: [[REGISTER]],93 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}94 ; CHECK: umull [[REGISTER:lr|r[0-9]+]],95 ; CHECK-NOT: [[REGISTER]],96 ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}97 %29 = udiv i32 %1, 1000000098 %30 = urem i32 %29, 1099 %31 = icmp ult i32 %30, 10100 %32 = trunc i32 %30 to i8101 %33 = or i8 %32, 48102 %34 = add i8 %32, 87103 %iftmp.5.0.7 = select i1 %31, i8 %33, i8 %34104 store volatile i8 %iftmp.5.0.7, ptr %p8, align 1105 %35 = udiv i32 %1, 100000000106 %36 = urem i32 %35, 10107 %37 = icmp ult i32 %36, 10108 %38 = trunc i32 %36 to i8109 %39 = or i8 %38, 48110 %40 = add i8 %38, 87111 %iftmp.5.0.8 = select i1 %37, i8 %39, i8 %40112 store volatile i8 %iftmp.5.0.8, ptr null, align 1113 br label %bb46114 115bb46: ; preds = %bb3116 ret void117}118 119declare noalias ptr @malloc() nounwind120 121declare i32 @ptou()122