31 lines · plain
1; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s2; Tests preRAsched support for VRegCycle interference.3 4target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32"5target triple = "thumbv7-apple-darwin10"6 7define void @t(i32 %src_width, ptr nocapture %src_copy_start, ptr nocapture %dst_copy_start, i32 %src_copy_start_index) nounwind optsize {8entry:9 %0 = icmp eq i32 %src_width, 010 br i1 %0, label %return, label %bb11 12; Make sure the scheduler schedules all uses of the preincrement13; induction variable before defining the postincrement value.14; CHECK-LABEL: t:15; CHECK: %bb16; CHECK-NOT: mov17bb: ; preds = %entry, %bb18 %j.05 = phi i32 [ %2, %bb ], [ 0, %entry ]19 %tmp = mul i32 %j.05, %src_copy_start_index20 %uglygep = getelementptr i8, ptr %src_copy_start, i32 %tmp21 %dst_copy_start_addr.03 = getelementptr float, ptr %dst_copy_start, i32 %j.0522 %1 = load float, ptr %uglygep, align 423 store float %1, ptr %dst_copy_start_addr.03, align 424 %2 = add i32 %j.05, 125 %exitcond = icmp eq i32 %2, %src_width26 br i1 %exitcond, label %return, label %bb27 28return: ; preds = %bb, %entry29 ret void30}31