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1; RUN: llc < %s -mcpu=cortex-a8 -verify-machineinstrs2; PR118293target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"4target triple = "armv7-none-linux-gnueabi"5 6define arm_aapcs_vfpcc void @foo(ptr nocapture %arg) nounwind uwtable align 2 {7bb:8 br i1 undef, label %bb1, label %bb29 10bb1: ; preds = %bb11 unreachable12 13bb2: ; preds = %bb14 br label %bb315 16bb3: ; preds = %bb4, %bb217 %tmp = icmp slt i32 undef, undef18 br i1 %tmp, label %bb4, label %bb6719 20bb4: ; preds = %bb321 %tmp5 = load <4 x i32>, ptr undef, align 1622 %tmp6 = and <4 x i32> %tmp5, <i32 8388607, i32 8388607, i32 8388607, i32 8388607>23 %tmp7 = or <4 x i32> %tmp6, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>24 %tmp8 = bitcast <4 x i32> %tmp7 to <4 x float>25 %constexpr = bitcast <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> to i12826 %constexpr1 = lshr i128 %constexpr, 6427 %constexpr2 = trunc i128 %constexpr1 to i6428 %constexpr3 = zext i64 %constexpr2 to i12829 %constexpr4 = shl i128 %constexpr3, 6430 %constexpr5 = bitcast <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> to i12831 %constexpr6 = trunc i128 %constexpr5 to i6432 %constexpr7 = zext i64 %constexpr6 to i12833 %or = or i128 %constexpr4, %constexpr734 %bc = bitcast i128 %or to <4 x float>35 %tmp9 = fsub <4 x float> %tmp8, %bc36 %tmp10 = fmul <4 x float> undef, %tmp937 %tmp11 = fadd <4 x float> undef, %tmp1038 %tmp12 = bitcast <4 x float> zeroinitializer to i12839 %tmp13 = lshr i128 %tmp12, 6440 %tmp14 = trunc i128 %tmp13 to i6441 %tmp15 = insertvalue [2 x i64] undef, i64 %tmp14, 142 %tmp16 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp11) #343 %tmp17 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp16, <4 x float> %tmp11) #344 %tmp18 = fmul <4 x float> %tmp17, %tmp1645 %tmp19 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp18, <4 x float> %tmp11) #346 %tmp20 = fmul <4 x float> %tmp19, %tmp1847 %tmp21 = fmul <4 x float> %tmp20, zeroinitializer48 %tmp22 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp21, <4 x float> undef) #349 call arm_aapcs_vfpcc void @bar(ptr null, ptr undef, ptr undef, [2 x i64] zeroinitializer) #350 %tmp23 = bitcast <4 x float> %tmp22 to i12851 %tmp24 = trunc i128 %tmp23 to i6452 %tmp25 = insertvalue [2 x i64] undef, i64 %tmp24, 053 %tmp26 = insertvalue [2 x i64] %tmp25, i64 0, 154 %tmp27 = load float, ptr undef, align 455 %tmp28 = insertelement <4 x float> undef, float %tmp27, i32 356 %tmp29 = load <4 x i32>, ptr undef, align 1657 %tmp30 = and <4 x i32> %tmp29, <i32 8388607, i32 8388607, i32 8388607, i32 8388607>58 %tmp31 = or <4 x i32> %tmp30, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>59 %tmp32 = bitcast <4 x i32> %tmp31 to <4 x float>60 %constexpr8 = bitcast <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> to i12861 %constexpr9 = lshr i128 %constexpr8, 6462 %constexpr10 = trunc i128 %constexpr9 to i6463 %constexpr11 = zext i64 %constexpr10 to i12864 %constexpr12 = shl i128 %constexpr11, 6465 %constexpr13 = bitcast <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> to i12866 %constexpr14 = trunc i128 %constexpr13 to i6467 %constexpr15 = zext i64 %constexpr14 to i12868 %or2 = or i128 %constexpr12, %constexpr1569 %bc2 = bitcast i128 %or2 to <4 x float>70 %tmp33 = fsub <4 x float> %tmp32, %bc271 %tmp34 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> undef, <4 x float> %tmp28) #372 %tmp35 = fmul <4 x float> %tmp34, undef73 %tmp36 = fmul <4 x float> %tmp35, undef74 %tmp37 = call arm_aapcs_vfpcc ptr undef(ptr undef) #375 %tmp38 = load float, ptr undef, align 476 %tmp39 = insertelement <2 x float> undef, float %tmp38, i32 077 %tmp40 = call arm_aapcs_vfpcc ptr undef(ptr undef) #378 %tmp41 = load float, ptr undef, align 479 %tmp42 = insertelement <4 x float> undef, float %tmp41, i32 380 %tmp43 = shufflevector <2 x float> %tmp39, <2 x float> undef, <4 x i32> zeroinitializer81 %tmp44 = fmul <4 x float> %tmp33, %tmp4382 %tmp45 = fadd <4 x float> %tmp42, %tmp4483 %tmp46 = fsub <4 x float> %tmp45, undef84 %tmp47 = fmul <4 x float> %tmp46, %tmp3685 %tmp48 = fadd <4 x float> undef, %tmp4786 %tmp49 = call arm_aapcs_vfpcc ptr undef(ptr undef) #387 %tmp50 = load float, ptr undef, align 488 %tmp51 = insertelement <4 x float> undef, float %tmp50, i32 389 %tmp52 = call arm_aapcs_vfpcc ptr null(ptr undef) #390 %tmp54 = load float, ptr %tmp52, align 491 %tmp55 = insertelement <4 x float> undef, float %tmp54, i32 392 %tmp56 = fsub <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %tmp2293 %tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) #394 %tmp58 = fmul <4 x float> undef, %tmp5795 %tmp59 = fsub <4 x float> %tmp51, %tmp4896 %tmp60 = fsub <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %tmp5897 %tmp61 = fmul <4 x float> %tmp59, %tmp6098 %tmp62 = fadd <4 x float> %tmp48, %tmp6199 call arm_aapcs_vfpcc void @baz(ptr undef, ptr undef, [2 x i64] %tmp26, ptr undef)100 %tmp63 = bitcast <4 x float> %tmp62 to i128101 %tmp64 = lshr i128 %tmp63, 64102 %tmp65 = trunc i128 %tmp64 to i64103 %tmp66 = insertvalue [2 x i64] zeroinitializer, i64 %tmp65, 1104 call arm_aapcs_vfpcc void @quux(ptr undef, ptr undef, [2 x i64] undef, ptr undef, [2 x i64] %tmp66, ptr undef, ptr undef, [2 x i64] %tmp26, [2 x i64] %tmp15, ptr undef)105 br label %bb3106 107bb67: ; preds = %bb3108 ret void109}110 111declare arm_aapcs_vfpcc void @bar(ptr, ptr, ptr, [2 x i64])112 113declare arm_aapcs_vfpcc void @baz(ptr, ptr nocapture, [2 x i64], ptr nocapture) nounwind uwtable inlinehint align 2114 115declare arm_aapcs_vfpcc void @quux(ptr, ptr, [2 x i64], ptr nocapture, [2 x i64], ptr nocapture, ptr nocapture, [2 x i64], [2 x i64], ptr nocapture) nounwind uwtable inlinehint align 2116 117declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone118 119declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone120 121declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone122