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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s3; rdar://110358954 5; DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) to6; (i16 load $addr+c*sizeof(i16)). It should have issued an extload instead. i.e.7; (i32 extload $addr+c*sizeof(i16)8define void @test_hi_short3(ptr nocapture %srcA, ptr nocapture %dst) nounwind {9; CHECK-LABEL: test_hi_short3:10; CHECK: @ %bb.0: @ %entry11; CHECK-NEXT: vldr d16, [r0]12; CHECK-NEXT: vmov.u16 r0, d16[2]13; CHECK-NEXT: vmov.32 d16[0], r014; CHECK-NEXT: vuzp.16 d16, d1715; CHECK-NEXT: vst1.32 {d16[0]}, [r1:32]16; CHECK-NEXT: bx lr17entry:18 %0 = load <3 x i16> , ptr %srcA, align 819 %1 = shufflevector <3 x i16> %0, <3 x i16> undef, <2 x i32> <i32 2, i32 undef>20 store <2 x i16> %1, ptr %dst, align 421 ret void22}23 24