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1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3; PR122814; Test generataion of code for vmull instruction when multiplying 128-bit5; vectors that were created by sign-extending smaller vector sizes.6;7; The vmull operation requires 64-bit vectors, so we must extend the original8; vector size to 64 bits for vmull operation.9; Previously failed with an assertion because the <4 x i8> vector was too small10; for vmull.11 12; Vector x Constant13; v4i814;15define void @sextload_v4i8_c(ptr %v) nounwind {16;CHECK-LABEL: sextload_v4i8_c:17entry:18 %0 = load <4 x i8>, ptr %v, align 819 %v0 = sext <4 x i8> %0 to <4 x i32>20;CHECK: vmull21 %v1 = mul <4 x i32> %v0, <i32 3, i32 3, i32 3, i32 3>22 store <4 x i32> %v1, ptr undef, align 823 ret void;24}25 26; v2i827;28define void @sextload_v2i8_c(ptr %v) nounwind {29;CHECK-LABEL: sextload_v2i8_c:30entry:31 %0 = load <2 x i8>, ptr %v, align 832 %v0 = sext <2 x i8> %0 to <2 x i64>33;CHECK: vmull34 %v1 = mul <2 x i64> %v0, <i64 3, i64 3>35 store <2 x i64> %v1, ptr undef, align 836 ret void;37}38 39; v2i1640;41define void @sextload_v2i16_c(ptr %v) nounwind {42;CHECK-LABEL: sextload_v2i16_c:43entry:44 %0 = load <2 x i16>, ptr %v, align 845 %v0 = sext <2 x i16> %0 to <2 x i64>46;CHECK: vmull47 %v1 = mul <2 x i64> %v0, <i64 3, i64 3>48 store <2 x i64> %v1, ptr undef, align 849 ret void;50}51 52 53; Vector x Vector54; v4i855;56define void @sextload_v4i8_v(ptr %v, ptr %p) nounwind {57;CHECK-LABEL: sextload_v4i8_v:58entry:59 %0 = load <4 x i8>, ptr %v, align 860 %v0 = sext <4 x i8> %0 to <4 x i32>61 62 %1 = load <4 x i8>, ptr %p, align 863 %v2 = sext <4 x i8> %1 to <4 x i32>64;CHECK: vmull65 %v1 = mul <4 x i32> %v0, %v266 store <4 x i32> %v1, ptr undef, align 867 ret void;68}69 70; v2i871;72define void @sextload_v2i8_v(ptr %v, ptr %p) nounwind {73;CHECK-LABEL: sextload_v2i8_v:74entry:75 %0 = load <2 x i8>, ptr %v, align 876 %v0 = sext <2 x i8> %0 to <2 x i64>77 78 %1 = load <2 x i8>, ptr %p, align 879 %v2 = sext <2 x i8> %1 to <2 x i64>80;CHECK: vmull81 %v1 = mul <2 x i64> %v0, %v282 store <2 x i64> %v1, ptr undef, align 883 ret void;84}85 86; v2i1687;88define void @sextload_v2i16_v(ptr %v, ptr %p) nounwind {89;CHECK-LABEL: sextload_v2i16_v:90entry:91 %0 = load <2 x i16>, ptr %v, align 892 %v0 = sext <2 x i16> %0 to <2 x i64>93 94 %1 = load <2 x i16>, ptr %p, align 895 %v2 = sext <2 x i16> %1 to <2 x i64>96;CHECK: vmull97 %v1 = mul <2 x i64> %v0, %v298 store <2 x i64> %v1, ptr undef, align 899 ret void;100}101 102 103; Vector(small) x Vector(big)104; v4i8 x v4i16105;106define void @sextload_v4i8_vs(ptr %v, ptr %p) nounwind {107;CHECK-LABEL: sextload_v4i8_vs:108entry:109 %0 = load <4 x i8>, ptr %v, align 8110 %v0 = sext <4 x i8> %0 to <4 x i32>111 112 %1 = load <4 x i16>, ptr %p, align 8113 %v2 = sext <4 x i16> %1 to <4 x i32>114;CHECK: vmull115 %v1 = mul <4 x i32> %v0, %v2116 store <4 x i32> %v1, ptr undef, align 8117 ret void;118}119 120; v2i8121; v2i8 x v2i16122define void @sextload_v2i8_vs(ptr %v, ptr %p) nounwind {123;CHECK-LABEL: sextload_v2i8_vs:124entry:125 %0 = load <2 x i8>, ptr %v, align 8126 %v0 = sext <2 x i8> %0 to <2 x i64>127 128 %1 = load <2 x i16>, ptr %p, align 8129 %v2 = sext <2 x i16> %1 to <2 x i64>130;CHECK: vmull131 %v1 = mul <2 x i64> %v0, %v2132 store <2 x i64> %v1, ptr undef, align 8133 ret void;134}135 136; v2i16137; v2i16 x v2i32138define void @sextload_v2i16_vs(ptr %v, ptr %p) nounwind {139;CHECK-LABEL: sextload_v2i16_vs:140entry:141 %0 = load <2 x i16>, ptr %v, align 8142 %v0 = sext <2 x i16> %0 to <2 x i64>143 144 %1 = load <2 x i32>, ptr %p, align 8145 %v2 = sext <2 x i32> %1 to <2 x i64>146;CHECK: vmull147 %v1 = mul <2 x i64> %v0, %v2148 store <2 x i64> %v1, ptr undef, align 8149 ret void;150}151