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1; RUN: llc < %s -mcpu=cortex-a82; Test that this doesn't crash.3; <rdar://problem/12183003>4 5target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"6target triple = "thumbv7-apple-ios5.1.0"7 8declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0(ptr, i32) nounwind readonly9 10declare void @llvm.arm.neon.vst1.p0.v16i8(ptr, <16 x i8>, i32) nounwind11 12define void @findEdges(ptr) nounwind ssp {13 %2 = icmp sgt i32 undef, 014 br i1 %2, label %5, label %315 16; <label>:3 ; preds = %5, %117 %4 = phi ptr [ %0, %1 ], [ %19, %5 ]18 ret void19 20; <label>:5 ; preds = %5, %121 %6 = phi ptr [ %19, %5 ], [ %0, %1 ]22 %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0(ptr null, i32 1)23 %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %7, 024 %9 = getelementptr inbounds i8, ptr null, i32 325 %10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0(ptr %9, i32 1)26 %11 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %10, 227 %12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0(ptr %6, i32 1)28 %13 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 029 %14 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 130 %15 = getelementptr inbounds i8, ptr %6, i32 331 %16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0(ptr %15, i32 1)32 %17 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 133 %18 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 234 %19 = getelementptr inbounds i8, ptr %6, i32 4835 %20 = bitcast <16 x i8> %13 to <2 x i64>36 %21 = bitcast <16 x i8> %8 to <2 x i64>37 %22 = bitcast <16 x i8> %14 to <2 x i64>38 %23 = shufflevector <2 x i64> %22, <2 x i64> undef, <1 x i32> zeroinitializer39 %24 = bitcast <1 x i64> %23 to <8 x i8>40 %25 = zext <8 x i8> %24 to <8 x i16>41 %26 = sub <8 x i16> zeroinitializer, %2542 %27 = bitcast <16 x i8> %17 to <2 x i64>43 %28 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %26) nounwind44 %29 = mul <8 x i16> %28, %2845 %30 = add <8 x i16> zeroinitializer, %2946 %31 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> undef, <8 x i16> %30) nounwind47 %32 = bitcast <16 x i8> %11 to <2 x i64>48 %33 = shufflevector <2 x i64> %32, <2 x i64> undef, <1 x i32> zeroinitializer49 %34 = bitcast <1 x i64> %33 to <8 x i8>50 %35 = zext <8 x i8> %34 to <8 x i16>51 %36 = sub <8 x i16> %35, zeroinitializer52 %37 = bitcast <16 x i8> %18 to <2 x i64>53 %38 = shufflevector <2 x i64> %37, <2 x i64> undef, <1 x i32> zeroinitializer54 %39 = bitcast <1 x i64> %38 to <8 x i8>55 %40 = zext <8 x i8> %39 to <8 x i16>56 %41 = sub <8 x i16> zeroinitializer, %4057 %42 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %36) nounwind58 %43 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %41) nounwind59 %44 = mul <8 x i16> %42, %4260 %45 = mul <8 x i16> %43, %4361 %46 = add <8 x i16> %45, %4462 %47 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %31, <8 x i16> %46) nounwind63 %48 = bitcast <8 x i16> %47 to <2 x i64>64 %49 = shufflevector <2 x i64> %48, <2 x i64> undef, <1 x i32> zeroinitializer65 %50 = bitcast <1 x i64> %49 to <4 x i16>66 %51 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %50, <4 x i16> undef) nounwind67 %52 = tail call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %51, <4 x i32> <i32 -6, i32 -6, i32 -6, i32 -6>)68 %53 = bitcast <4 x i16> %52 to <1 x i64>69 %54 = shufflevector <1 x i64> %53, <1 x i64> undef, <2 x i32> <i32 0, i32 1>70 %55 = bitcast <2 x i64> %54 to <8 x i16>71 %56 = tail call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %55, <8 x i16> <i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8>)72 %57 = shufflevector <2 x i64> %20, <2 x i64> undef, <1 x i32> <i32 1>73 %58 = bitcast <1 x i64> %57 to <8 x i8>74 %59 = zext <8 x i8> %58 to <8 x i16>75 %60 = sub <8 x i16> zeroinitializer, %5976 %61 = shufflevector <2 x i64> %21, <2 x i64> undef, <1 x i32> <i32 1>77 %62 = bitcast <1 x i64> %61 to <8 x i8>78 %63 = zext <8 x i8> %62 to <8 x i16>79 %64 = sub <8 x i16> %63, zeroinitializer80 %65 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %60) nounwind81 %66 = mul <8 x i16> %65, %6582 %67 = add <8 x i16> zeroinitializer, %6683 %68 = shufflevector <2 x i64> %27, <2 x i64> undef, <1 x i32> <i32 1>84 %69 = bitcast <1 x i64> %68 to <8 x i8>85 %70 = zext <8 x i8> %69 to <8 x i16>86 %71 = sub <8 x i16> zeroinitializer, %7087 %72 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> undef) nounwind88 %73 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %71) nounwind89 %74 = mul <8 x i16> %72, %7290 %75 = mul <8 x i16> %73, %7391 %76 = add <8 x i16> %75, %7492 %77 = shufflevector <2 x i64> %32, <2 x i64> undef, <1 x i32> <i32 1>93 %78 = bitcast <1 x i64> %77 to <8 x i8>94 %79 = zext <8 x i8> %78 to <8 x i16>95 %80 = sub <8 x i16> %79, zeroinitializer96 %81 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %80) nounwind97 %82 = mul <8 x i16> %81, %8198 %83 = add <8 x i16> zeroinitializer, %8299 %84 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %76, <8 x i16> %83) nounwind100 %85 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %67, <8 x i16> %84) nounwind101 %86 = bitcast <8 x i16> %85 to <2 x i64>102 %87 = shufflevector <2 x i64> %86, <2 x i64> undef, <1 x i32> <i32 1>103 %88 = bitcast <1 x i64> %87 to <4 x i16>104 %89 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %88, <4 x i16> undef) nounwind105 %90 = tail call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %89, <4 x i32> <i32 -6, i32 -6, i32 -6, i32 -6>)106 %91 = bitcast <4 x i16> %90 to <1 x i64>107 %92 = shufflevector <1 x i64> undef, <1 x i64> %91, <2 x i32> <i32 0, i32 1>108 %93 = bitcast <2 x i64> %92 to <8 x i16>109 %94 = tail call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %93, <8 x i16> <i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8>)110 %95 = bitcast <8 x i8> %56 to <1 x i64>111 %96 = bitcast <8 x i8> %94 to <1 x i64>112 %97 = shufflevector <1 x i64> %95, <1 x i64> %96, <2 x i32> <i32 0, i32 1>113 %98 = bitcast <2 x i64> %97 to <16 x i8>114 tail call void @llvm.arm.neon.vst1.p0.v16i8(ptr null, <16 x i8> %98, i32 1)115 %99 = icmp slt i32 undef, undef116 br i1 %99, label %5, label %3117}118 119declare <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone120 121declare <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone122 123declare <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone124 125declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone126 127declare <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone128 129declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) nounwind readnone130