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1; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE2; RUN: llc -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -global-isel-abort=0 -enable-arm-gisel-bigendian -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=BIG3 4define void @test_void_return() {5; CHECK-LABEL: name: test_void_return6; CHECK: BX_RET 14 /* CC::al */, $noreg7entry:8 ret void9}10 11define signext i1 @test_add_i1(i1 %x, i1 %y) {12; CHECK-LABEL: name: test_add_i113; CHECK: liveins: $r0, $r114; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r015; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR0]]16; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r117; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR1]]18; CHECK: [[SUM:%[0-9]+]]:_(s1) = G_ADD [[VREGX]], [[VREGY]]19; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_SEXT [[SUM]]20; CHECK: $r0 = COPY [[EXT]](s32)21; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r022entry:23 %sum = add i1 %x, %y24 ret i1 %sum25}26 27define i8 @test_add_i8(i8 %x, i8 %y) {28; CHECK-LABEL: name: test_add_i829; CHECK: liveins: $r0, $r130; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r031; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]32; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r133; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]]34; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGX]], [[VREGY]]35; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]36; CHECK: $r0 = COPY [[SUM_EXT]](s32)37; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r038entry:39 %sum = add i8 %x, %y40 ret i8 %sum41}42 43define i8 @test_sub_i8(i8 %x, i8 %y) {44; CHECK-LABEL: name: test_sub_i845; CHECK: liveins: $r0, $r146; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r047; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]48; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r149; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]]50; CHECK: [[RES:%[0-9]+]]:_(s8) = G_SUB [[VREGX]], [[VREGY]]51; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]52; CHECK: $r0 = COPY [[RES_EXT]](s32)53; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r054entry:55 %res = sub i8 %x, %y56 ret i8 %res57}58 59define signext i8 @test_return_sext_i8(i8 %x) {60; CHECK-LABEL: name: test_return_sext_i861; CHECK: liveins: $r062; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r063; CHECK: [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]64; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_SEXT [[VREG]]65; CHECK: $r0 = COPY [[VREGEXT]](s32)66; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r067entry:68 ret i8 %x69}70 71define i16 @test_add_i16(i16 %x, i16 %y) {72; CHECK-LABEL: name: test_add_i1673; CHECK: liveins: $r0, $r174; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r075; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]76; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r177; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]78; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGX]], [[VREGY]]79; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]80; CHECK: $r0 = COPY [[SUM_EXT]](s32)81; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r082entry:83 %sum = add i16 %x, %y84 ret i16 %sum85}86 87define i16 @test_sub_i16(i16 %x, i16 %y) {88; CHECK-LABEL: name: test_sub_i1689; CHECK: liveins: $r0, $r190; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r091; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]92; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r193; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]94; CHECK: [[RES:%[0-9]+]]:_(s16) = G_SUB [[VREGX]], [[VREGY]]95; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]96; CHECK: $r0 = COPY [[RES_EXT]](s32)97; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r098entry:99 %res = sub i16 %x, %y100 ret i16 %res101}102 103define zeroext i16 @test_return_zext_i16(i16 %x) {104; CHECK-LABEL: name: test_return_zext_i16105; CHECK: liveins: $r0106; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0107; CHECK: [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]108; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREG]]109; CHECK: $r0 = COPY [[VREGEXT]](s32)110; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0111entry:112 ret i16 %x113}114 115define i32 @test_add_i32(i32 %x, i32 %y) {116; CHECK-LABEL: name: test_add_i32117; CHECK: liveins: $r0, $r1118; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY $r0119; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY $r1120; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGX]], [[VREGY]]121; CHECK: $r0 = COPY [[SUM]](s32)122; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0123entry:124 %sum = add i32 %x, %y125 ret i32 %sum126}127 128define i32 @test_sub_i32(i32 %x, i32 %y) {129; CHECK-LABEL: name: test_sub_i32130; CHECK: liveins: $r0, $r1131; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY $r0132; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY $r1133; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SUB [[VREGX]], [[VREGY]]134; CHECK: $r0 = COPY [[RES]](s32)135; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0136entry:137 %res = sub i32 %x, %y138 ret i32 %res139}140 141define i32 @test_stack_args(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) {142; CHECK-LABEL: name: test_stack_args143; CHECK: fixedStack:144; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4145; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4146; CHECK: liveins: $r0, $r1, $r2, $r3147; CHECK: [[VREGP2:%[0-9]+]]:_(s32) = COPY $r2148; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]149; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]]{{.*}}load (s32)150; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGP2]], [[VREGP5]]151; CHECK: $r0 = COPY [[SUM]]152; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0153entry:154 %sum = add i32 %p2, %p5155 ret i32 %sum156}157 158define i16 @test_stack_args_signext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,159 i8 signext %p4, i16 signext %p5) {160; CHECK-LABEL: name: test_stack_args_signext161; CHECK: fixedStack:162; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4163; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4164; CHECK: liveins: $r0, $r1, $r2, $r3165; CHECK: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1166; CHECK: [[VREGP1:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]167; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]168; CHECK: [[VREGP5EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load (s32)169; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[VREGP5EXT]], 16170; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]]171; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGP1]], [[VREGP5]]172; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]173; CHECK: $r0 = COPY [[SUM_EXT]](s32)174; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0175entry:176 %sum = add i16 %p1, %p5177 ret i16 %sum178}179 180define i8 @test_stack_args_zeroext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,181 i8 zeroext %p4, i16 zeroext %p5) {182; CHECK-LABEL: name: test_stack_args_zeroext183; CHECK: fixedStack:184; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4185; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4186; CHECK: liveins: $r0, $r1, $r2, $r3187; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY $r2188; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]]189; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]]190; CHECK: [[VREGP4EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP4]](p0){{.*}}load (s32)191; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[VREGP4EXT]], 8192; CHECK: [[VREGP4:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_ZEXT]]193; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]]194; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]195; CHECK: $r0 = COPY [[SUM_EXT]](s32)196; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0197entry:198 %sum = add i8 %p2, %p4199 ret i8 %sum200}201 202define i8 @test_stack_args_noext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,203 i8 %p4, i16 %p5) {204; CHECK-LABEL: name: test_stack_args_noext205; CHECK: fixedStack:206; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0, size: 4, alignment: 8,207; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4, size: 4, alignment: 4,208; CHECK: liveins: $r0, $r1, $r2, $r3209; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY $r2210; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]]211; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]]212; CHECK: [[VREGP4:%[0-9]+]]:_(s32) = G_LOAD [[FIP4]](p0){{.*}}load (s32)213; CHECK: [[TRUNC_VREGP4:%[0-9]+]]:_(s8) = G_TRUNC [[VREGP4]]214; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[TRUNC_VREGP4]]215; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]216; CHECK: $r0 = COPY [[SUM_EXT]](s32)217; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0218entry:219 %sum = add i8 %p2, %p4220 ret i8 %sum221}222 223define zeroext i16 @test_stack_args_extend_the_extended(i32 %p0, i16 %p1, i8 %p2, i1 %p3,224 i8 signext %p4, i16 signext %p5) {225; CHECK-LABEL: name: test_stack_args_extend_the_extended226; CHECK: fixedStack:227; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4, alignment: 8228; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4, alignment: 4229; CHECK: liveins: $r0, $r1, $r2, $r3230; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]231; CHECK: [[VREGP5SEXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load (s32)232; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[VREGP5SEXT]], 16233; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]]234; CHECK: [[VREGP5ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREGP5]]235; CHECK: $r0 = COPY [[VREGP5ZEXT]]236; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0237entry:238 ret i16 %p5239}240 241define i16 @test_ptr_arg(ptr %p) {242; CHECK-LABEL: name: test_ptr_arg243; CHECK: liveins: $r0244; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY $r0245; CHECK: [[VREGV:%[0-9]+]]:_(s16) = G_LOAD [[VREGP]](p0){{.*}}load (s16)246entry:247 %v = load i16, ptr %p248 ret i16 %v249}250 251define ptr @test_ptr_ret(ptr %p) {252; Test pointer returns and pointer-to-pointer arguments253; CHECK-LABEL: name: test_ptr_ret254; CHECK: liveins: $r0255; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY $r0256; CHECK: [[VREGV:%[0-9]+]]:_(p0) = G_LOAD [[VREGP]](p0){{.*}}load (p0)257; CHECK: $r0 = COPY [[VREGV]]258; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0259entry:260 %v = load ptr, ptr %p261 ret ptr %v262}263 264define i32 @test_ptr_arg_on_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, ptr %p) {265; CHECK-LABEL: name: test_ptr_arg_on_stack266; CHECK: fixedStack:267; CHECK: id: [[P:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4268; CHECK: liveins: $r0, $r1, $r2, $r3269; CHECK: [[FIP:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P]]270; CHECK: [[VREGP:%[0-9]+]]:_(p0) = G_LOAD [[FIP]](p0){{.*}}load (p0)271; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_LOAD [[VREGP]](p0){{.*}}load (s32)272; CHECK: $r0 = COPY [[VREGV]]273; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0274entry:275 %v = load i32, ptr %p276 ret i32 %v277}278 279define arm_aapcscc float @test_float_aapcscc(float %p0, float %p1, float %p2,280 float %p3, float %p4, float %p5) {281; CHECK-LABEL: name: test_float_aapcscc282; CHECK: fixedStack:283; CHECK-DAG: id: [[P4:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4284; CHECK-DAG: id: [[P5:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4285; CHECK: liveins: $r0, $r1, $r2, $r3286; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY $r1287; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]288; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load (s32)289; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGP5]]290; CHECK: $r0 = COPY [[VREGV]]291; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0292entry:293 %v = fadd float %p1, %p5294 ret float %v295}296 297define arm_aapcs_vfpcc float @test_float_vfpcc(float %p0, float %p1, float %p2,298 float %p3, float %p4, float %p5,299 float %ridiculous,300 float %number,301 float %of,302 float %parameters,303 float %that,304 float %should,305 float %never,306 float %exist,307 float %in,308 float %practice,309 float %q0, float %q1) {310; CHECK-LABEL: name: test_float_vfpcc311; CHECK: fixedStack:312; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4313; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4314; CHECK: liveins: $s0, $s1, $s2, $s3, $s4, $s5, $s6, $s7, $s8, $s9, $s10, $s11, $s12, $s13, $s14, $s15315; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY $s1316; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]317; CHECK: [[VREGQ1:%[0-9]+]]:_(s32) = G_LOAD [[FIQ1]](p0){{.*}}load (s32)318; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGQ1]]319; CHECK: $s0 = COPY [[VREGV]]320; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0321entry:322 %v = fadd float %p1, %q1323 ret float %v324}325 326define arm_aapcs_vfpcc double @test_double_vfpcc(double %p0, double %p1, double %p2,327 double %p3, double %p4, double %p5,328 double %reasonable,329 double %parameters,330 double %q0, double %q1) {331; CHECK-LABEL: name: test_double_vfpcc332; CHECK: fixedStack:333; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8334; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8335; CHECK: liveins: $d0, $d1, $d2, $d3, $d4, $d5, $d6, $d7336; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY $d1337; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]338; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load (s64)339; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]340; CHECK: $d0 = COPY [[VREGV]]341; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0342entry:343 %v = fadd double %p1, %q1344 ret double %v345}346 347define arm_aapcscc double @test_double_aapcscc(double %p0, double %p1, double %p2,348 double %p3, double %p4, double %p5) {349; CHECK-LABEL: name: test_double_aapcscc350; CHECK: fixedStack:351; CHECK-DAG: id: [[P2:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8352; CHECK-DAG: id: [[P3:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8353; CHECK-DAG: id: [[P4:[0-9]+]]{{.*}}offset: 16{{.*}}size: 8354; CHECK-DAG: id: [[P5:[0-9]+]]{{.*}}offset: 24{{.*}}size: 8355; CHECK: liveins: $r0, $r1, $r2, $r3356; CHECK-DAG: [[VREGP1LO:%[0-9]+]]:_(s32) = COPY $r2357; CHECK-DAG: [[VREGP1HI:%[0-9]+]]:_(s32) = COPY $r3358; LITTLE: [[VREGP1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP1LO]](s32), [[VREGP1HI]](s32)359; BIG: [[VREGP1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP1HI]](s32), [[VREGP1LO]](s32)360; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]361; CHECK: [[VREGP5:%[0-9]+]]:_(s64) = G_LOAD [[FIP5]](p0){{.*}}load (s64)362; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGP5]]363; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)364; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)365; CHECK-DAG: $r0 = COPY [[VREGVLO]]366; CHECK-DAG: $r1 = COPY [[VREGVHI]]367; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1368entry:369 %v = fadd double %p1, %p5370 ret double %v371}372 373define arm_aapcs_vfpcc double @test_double_gap_vfpcc(double %p0, float %filler,374 double %p1, double %p2,375 double %p3, double %p4,376 double %reasonable,377 double %parameters,378 double %q0, double %q1) {379; CHECK-LABEL: name: test_double_gap_vfpcc380; CHECK: fixedStack:381; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8382; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8383; CHECK: liveins: $d0, $d2, $d3, $d4, $d5, $d6, $d7, $s2384; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY $d2385; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]386; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load (s64)387; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]388; CHECK: $d0 = COPY [[VREGV]]389; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0390entry:391 %v = fadd double %p1, %q1392 ret double %v393}394 395define arm_aapcscc double @test_double_gap_aapcscc(float %filler, double %p0,396 double %p1) {397; CHECK-LABEL: name: test_double_gap_aapcscc398; CHECK: fixedStack:399; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8400; CHECK: liveins: $r0, $r2, $r3401; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY $r2402; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY $r3403; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)404; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)405; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]]406; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = G_LOAD [[FIP1]](p0){{.*}}load (s64)407; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]]408; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)409; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)410; CHECK-DAG: $r0 = COPY [[VREGVLO]]411; CHECK-DAG: $r1 = COPY [[VREGVHI]]412; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1413entry:414 %v = fadd double %p0, %p1415 ret double %v416}417 418define arm_aapcscc double @test_double_gap2_aapcscc(double %p0, float %filler,419 double %p1) {420; CHECK-LABEL: name: test_double_gap2_aapcscc421; CHECK: fixedStack:422; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8423; CHECK: liveins: $r0, $r1, $r2424; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY $r0425; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY $r1426; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)427; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)428; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]]429; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = G_LOAD [[FIP1]](p0){{.*}}load (s64)430; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]]431; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)432; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)433; CHECK-DAG: $r0 = COPY [[VREGVLO]]434; CHECK-DAG: $r1 = COPY [[VREGVHI]]435; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1436entry:437 %v = fadd double %p0, %p1438 ret double %v439}440 441define i32 @test_shufflevector_s32_v2s32(i32 %arg) {442; CHECK-LABEL: name: test_shufflevector_s32_v2s32443; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $r0444; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ARG]](s32), [[ARG]](s32)445; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>)446 %vec = insertelement <1 x i32> undef, i32 %arg, i32 0447 %shuffle = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer448 %res = extractelement <2 x i32> %shuffle, i32 0449 ret i32 %res450}451 452define i32 @test_shufflevector_s32_s32_s32(i32 %arg) {453; CHECK-LABEL: name: test_shufflevector_s32_s32_s32454; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $r0455; CHECK: r0 = COPY [[ARG]](s32)456 %vec = insertelement <1 x i32> undef, i32 %arg, i32 0457 %shuffle = shufflevector <1 x i32> %vec, <1 x i32> undef, <1 x i32> zeroinitializer458 %res = extractelement <1 x i32> %shuffle, i32 0459 ret i32 %res460}461 462define i32 @test_shufflevector_v2s32_v3s32(i32 %arg1, i32 %arg2) {463; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32464; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $r0465; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY $r1466; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF467; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0468; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1469; CHECK-DAG: [[V1:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)470; CHECK-DAG: [[V2:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)471; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_SHUFFLE_VECTOR [[V2]](<2 x s32>), [[UNDEF]], shufflemask(1, 0, 1)472; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)473 %v1 = insertelement <2 x i32> undef, i32 %arg1, i32 0474 %v2 = insertelement <2 x i32> %v1, i32 %arg2, i32 1475 %shuffle = shufflevector <2 x i32> %v2, <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1>476 %res = extractelement <3 x i32> %shuffle, i32 0477 ret i32 %res478}479 480 481define i32 @test_shufflevector_v2s32_v4s32(i32 %arg1, i32 %arg2) {482; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32483; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $r0484; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY $r1485; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF486; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0487; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1488; CHECK-DAG: [[V1:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)489; CHECK-DAG: [[V2:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)490; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[V2]](<2 x s32>), [[UNDEF]], shufflemask(0, 0, 0, 0)491; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<4 x s32>)492 %v1 = insertelement <2 x i32> undef, i32 %arg1, i32 0493 %v2 = insertelement <2 x i32> %v1, i32 %arg2, i32 1494 %shuffle = shufflevector <2 x i32> %v2, <2 x i32> undef, <4 x i32> zeroinitializer495 %res = extractelement <4 x i32> %shuffle, i32 0496 ret i32 %res497}498 499define i32 @test_shufflevector_v4s32_v2s32(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {500; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32501; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $r0502; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY $r1503; CHECK: [[ARG3:%[0-9]+]]:_(s32) = COPY $r2504; CHECK: [[ARG4:%[0-9]+]]:_(s32) = COPY $r3505; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF506; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0507; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1508; CHECK-DAG: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2509; CHECK-DAG: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3510; CHECK-DAG: [[V1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)511; CHECK-DAG: [[V2:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)512; CHECK-DAG: [[V3:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[V2]], [[ARG3]](s32), [[C2]](s32)513; CHECK-DAG: [[V4:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[V3]], [[ARG4]](s32), [[C3]](s32)514; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[V4]](<4 x s32>), [[UNDEF]], shufflemask(1, 3)515; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>)516 %v1 = insertelement <4 x i32> undef, i32 %arg1, i32 0517 %v2 = insertelement <4 x i32> %v1, i32 %arg2, i32 1518 %v3 = insertelement <4 x i32> %v2, i32 %arg3, i32 2519 %v4 = insertelement <4 x i32> %v3, i32 %arg4, i32 3520 %shuffle = shufflevector <4 x i32> %v4, <4 x i32> undef, <2 x i32> <i32 1, i32 3>521 %res = extractelement <2 x i32> %shuffle, i32 0522 ret i32 %res523}524 525%struct.v2s32 = type { <2 x i32> }526 527define i32 @test_constantstruct_v2s32() {528; CHECK-LABEL: name: test_constantstruct_v2s32529; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1530; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2531; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C2]](s32)532; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0533; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[C3]]534 %vec = extractvalue %struct.v2s32 {<2 x i32><i32 1, i32 2>}, 0535 %elt = extractelement <2 x i32> %vec, i32 0536 ret i32 %elt537}538 539%struct.v2s32.s32.s32 = type { <2 x i32>, i32, i32 }540 541define i32 @test_constantstruct_v2s32_s32_s32() {542; CHECK-LABEL: name: test_constantstruct_v2s32_s32_s32543; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1544; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2545; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C2]](s32)546; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3547; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4548; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0549; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[C5]](s32)550 %vec = extractvalue %struct.v2s32.s32.s32 {<2 x i32><i32 1, i32 2>, i32 3, i32 4}, 0551 %elt = extractelement <2 x i32> %vec, i32 0552 ret i32 %elt553}554 555define void @test_load_store_struct(ptr %addr) {556; Make sure the IRTranslator doesn't use an unnecessarily large GEP index type557; when breaking up loads and stores of aggregates.558; CHECK-LABEL: name: test_load_store_struct559; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $r0560; CHECK-DAG: [[VAL1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load (s32) from %ir.addr)561; CHECK-DAG: [[OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 4562; CHECK-DAG: [[ADDR2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR1]], [[OFFSET]](s32)563; CHECK-DAG: [[VAL2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load (s32) from %ir.addr + 4)564; CHECK-DAG: G_STORE [[VAL1]](s32), [[ADDR1]](p0) :: (store (s32) into %ir.addr)565; CHECK-DAG: [[ADDR3:%[0-9]+]]:_(p0) = COPY [[ADDR2]]566; CHECK-DAG: G_STORE [[VAL2]](s32), [[ADDR3]](p0) :: (store (s32) into %ir.addr + 4)567 %val = load {i32, i32}, ptr %addr, align 4568 store {i32, i32} %val, ptr %addr, align 4569 ret void570}571