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1; RUN: llc -mtriple arm-linux-gnueabihf -mattr=+vfp2 -float-abi=hard -global-isel %s -o - | FileCheck %s -check-prefix CHECK -check-prefix HARD2; RUN: llc -mtriple arm-linux-gnueabi -mattr=+vfp2,+soft-float -float-abi=soft -global-isel %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT-AEABI3; RUN: llc -mtriple arm-linux-gnu- -mattr=+vfp2,+soft-float -float-abi=soft -global-isel %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT-DEFAULT4 5define arm_aapcscc float @test_frem_float(float %x, float %y) {6; CHECK-LABEL: test_frem_float:7; CHECK: bl fmodf8 %r = frem float %x, %y9 ret float %r10}11 12define arm_aapcscc double @test_frem_double(double %x, double %y) {13; CHECK-LABEL: test_frem_double:14; CHECK: bl fmod15 %r = frem double %x, %y16 ret double %r17}18 19declare float @llvm.pow.f32(float %x, float %y)20define arm_aapcscc float @test_fpow_float(float %x, float %y) {21; CHECK-LABEL: test_fpow_float:22; CHECK: bl powf23 %r = call float @llvm.pow.f32(float %x, float %y)24 ret float %r25}26 27declare double @llvm.pow.f64(double %x, double %y)28define arm_aapcscc double @test_fpow_double(double %x, double %y) {29; CHECK-LABEL: test_fpow_double:30; CHECK: bl pow31 %r = call double @llvm.pow.f64(double %x, double %y)32 ret double %r33}34 35define arm_aapcscc float @test_add_float(float %x, float %y) {36; CHECK-LABEL: test_add_float:37; HARD: vadd.f3238; SOFT-AEABI: bl __aeabi_fadd39; SOFT-DEFAULT: bl __addsf340 %r = fadd float %x, %y41 ret float %r42}43 44define arm_aapcscc double @test_add_double(double %x, double %y) {45; CHECK-LABEL: test_add_double:46; HARD: vadd.f6447; SOFT-AEABI: bl __aeabi_dadd48; SOFT-DEFAULT: bl __adddf349 %r = fadd double %x, %y50 ret double %r51}52 53define arm_aapcscc float @test_sub_float(float %x, float %y) {54; CHECK-LABEL: test_sub_float:55; HARD: vsub.f3256; SOFT-AEABI: bl __aeabi_fsub57; SOFT-DEFAULT: bl __subsf358 %r = fsub float %x, %y59 ret float %r60}61 62define arm_aapcscc double @test_sub_double(double %x, double %y) {63; CHECK-LABEL: test_sub_double:64; HARD: vsub.f6465; SOFT-AEABI: bl __aeabi_dsub66; SOFT-DEFAULT: bl __subdf367 %r = fsub double %x, %y68 ret double %r69}70define arm_aapcs_vfpcc i32 @test_cmp_float_ogt(float %x, float %y) {71; CHECK-LABEL: test_cmp_float_ogt72; HARD: vcmp.f3273; HARD: vmrs APSR_nzcv, fpscr74; HARD-NEXT: movgt75; SOFT-AEABI: bl __aeabi_fcmpgt76; SOFT-DEFAULT: bl __gtsf277entry:78 %v = fcmp ogt float %x, %y79 %r = zext i1 %v to i3280 ret i32 %r81}82 83define arm_aapcs_vfpcc i32 @test_cmp_float_one(float %x, float %y) {84; CHECK-LABEL: test_cmp_float_one85; HARD: vcmp.f3286; HARD: vmrs APSR_nzcv, fpscr87; HARD: movgt88; HARD-NOT: vcmp89; HARD: movmi90; SOFT-AEABI-DAG: bl __aeabi_fcmpgt91; SOFT-AEABI-DAG: bl __aeabi_fcmplt92; SOFT-DEFAULT-DAG: bl __gtsf293; SOFT-DEFAULT-DAG: bl __ltsf294entry:95 %v = fcmp one float %x, %y96 %r = zext i1 %v to i3297 ret i32 %r98}99