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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple armv7-gnueabihf -run-pass instruction-select \3# RUN: -verify-machineinstrs -o - %s | FileCheck %s4---5# Test that we constrain register classes of temporary virtual registers6# defined by nested instructions built from a Dst Pattern7#8# G_FPTOSI selects to a (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR), where9# COPY_TO_REGCLASS doesn't constrain its source register class. It exposes the10# bug as we create a tmp reg for VTOSIZS' result and don't constrain its11# register class as COPY_TO_REGCLASS' source (which is fine) nor as VTOSIZS'12# destination (which is not).13#14# https://bugs.llvm.org/show_bug.cgi?id=3596515name: test_fptosi16legalized: true17regBankSelected: true18body: |19 bb.1:20 ; CHECK-LABEL: name: test_fptosi21 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s022 ; CHECK: [[VTOSIZS:%[0-9]+]]:spr = nofpexcept VTOSIZS [[COPY]], 14 /* CC::al */, $noreg23 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]]24 ; CHECK: $r0 = COPY [[COPY1]]25 ; CHECK: MOVPCLR 14 /* CC::al */, $noreg, implicit $r026 %0:fprb(s32) = COPY $s027 %1:gprb(s32) = G_FPTOSI %0(s32)28 $r0 = COPY %1(s32)29 MOVPCLR 14, $noreg, implicit $r030...31