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1# RUN: llc -O0 -mtriple arm-- -mattr=+vfp3,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP32# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+vfp3,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP33# RUN: llc -O0 -mtriple arm-- -mattr=+vfp2,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP24# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+vfp2,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,VFP25--- |6  define void @test_fpconst_zero_s32() { ret void }7  define void @test_fpconst_zero_s64() { ret void }8 9  define void @test_fpconst_8bit_s32() { ret void }10  define void @test_fpconst_8bit_s64() { ret void }11...12---13name:            test_fpconst_zero_s3214# CHECK-LABEL: name: test_fpconst_zero_s3215legalized:       true16regBankSelected: true17selected:        false18# CHECK: selected: true19registers:20  - { id: 0, class: gprb }21  - { id: 1, class: fprb }22# CHECK: constants:23# CHECK-NEXT: id: 024# CHECK-NEXT: value: 'float 0.000000e+00'25# CHECK-NEXT: alignment: 426# CHECK-NEXT: isTargetSpecific: false27body:             |28  bb.0:29    liveins: $r030 31    %0(p0) = COPY $r032    ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r033 34    %1(s32) = G_FCONSTANT float 0.035    ; CHECK: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)36 37    G_STORE %1(s32), %0 :: (store (s32))38    ; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg39 40    BX_RET 14, $noreg41    ; CHECK: BX_RET 14 /* CC::al */, $noreg42...43---44name:            test_fpconst_zero_s6445# CHECK-LABEL: name: test_fpconst_zero_s6446legalized:       true47regBankSelected: true48selected:        false49# CHECK: selected: true50registers:51  - { id: 0, class: gprb }52  - { id: 1, class: fprb }53# CHECK: constants:54# CHECK-NEXT: id: 055# CHECK-NEXT: value: 'double 0.000000e+00'56# CHECK-NEXT: alignment: 857# CHECK-NEXT: isTargetSpecific: false58body:             |59  bb.0:60    liveins: $r061 62    %0(p0) = COPY $r063    ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r064 65    %1(s64) = G_FCONSTANT double 0.066    ; CHECK: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14 /* CC::al */, $noreg :: (load (s64) from constant-pool)67 68    G_STORE %1(s64), %0 :: (store (s64))69    ; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg70 71    BX_RET 14, $noreg72    ; CHECK: BX_RET 14 /* CC::al */, $noreg73...74---75name:            test_fpconst_8bit_s3276# CHECK-LABEL: name: test_fpconst_8bit_s3277legalized:       true78regBankSelected: true79selected:        false80# CHECK: selected: true81registers:82  - { id: 0, class: gprb }83  - { id: 1, class: fprb }84# VFP3: constants: []85# VFP2: constants:86# VFP2-NEXT: id: 087# VFP2-NEXT: value: 'float -2.000000e+00'88# VFP2-NEXT: alignment: 489# VFP2-NEXT: isTargetSpecific: false90body:             |91  bb.0:92    liveins: $r093 94    %0(p0) = COPY $r095    ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r096 97    %1(s32) = G_FCONSTANT float -2.098    ; VFP3: [[VREG:%[0-9]+]]:spr = FCONSTS 128, 14 /* CC::al */, $noreg99    ; VFP2: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)100 101    G_STORE %1(s32), %0 :: (store (s32))102    ; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg103 104    BX_RET 14, $noreg105    ; CHECK: BX_RET 14 /* CC::al */, $noreg106...107---108name:            test_fpconst_8bit_s64109# CHECK-LABEL: name: test_fpconst_8bit_s64110legalized:       true111regBankSelected: true112selected:        false113# CHECK: selected: true114registers:115  - { id: 0, class: gprb }116  - { id: 1, class: fprb }117# VFP3: constants: []118# VFP2: constants:119# VFP2-NEXT: id: 0120# VFP2-NEXT: value: double 5.000000e-01121# VFP2-NEXT: alignment: 8122# VFP2-NEXT: isTargetSpecific: false123body:             |124  bb.0:125    liveins: $r0126 127    %0(p0) = COPY $r0128    ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0129 130    %1(s64) = G_FCONSTANT double 5.0e-1131    ; VFP3: [[VREG:%[0-9]+]]:dpr = FCONSTD 96, 14 /* CC::al */, $noreg132    ; VFP2: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14 /* CC::al */, $noreg :: (load (s64) from constant-pool)133 134    G_STORE %1(s64), %0 :: (store (s64))135    ; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14 /* CC::al */, $noreg136 137    BX_RET 14, $noreg138    ; CHECK: BX_RET 14 /* CC::al */, $noreg139...140