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1# RUN: llc -O0 -mtriple arm-- -mattr=+v6 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,ARM2# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,THUMB3--- |4 define void @test_shifts_to_revsh() { ret void }5 define void @test_shifts_to_revsh_commutative() { ret void }6 define void @test_shifts_no_revsh_constants() { ret void }7...8---9name: test_shifts_to_revsh10# CHECK-LABEL: name: test_shifts_to_revsh11legalized: true12regBankSelected: true13selected: false14# CHECK: selected: true15registers:16 - { id: 0, class: gprb }17 - { id: 1, class: gprb }18 - { id: 2, class: gprb }19 - { id: 3, class: gprb }20 - { id: 4, class: gprb }21 - { id: 5, class: gprb }22 - { id: 6, class: gprb }23 - { id: 7, class: gprb }24 - { id: 8, class: gprb }25 - { id: 9, class: gprb }26body: |27 bb.0:28 liveins: $r029 30 %0(s32) = COPY $r031 ; ARM: [[VREGX:%[0-9]+]]:gpr = COPY $r032 ; THUMB: [[VREGX:%[0-9]+]]:rgpr = COPY $r033 34 %1(s32) = G_CONSTANT i32 2435 %2(s32) = G_SHL %0(s32), %1(s32)36 37 %3(s32) = G_CONSTANT i32 1638 %4(s32) = G_ASHR %2(s32), %3(s32)39 40 %5(s32) = G_CONSTANT i32 841 %6(s32) = G_LSHR %0(s32), %5(s32)42 43 %7(s32) = G_CONSTANT i32 25544 %8(s32) = G_AND %6(s32), %7(s32)45 46 %9(s32) = G_OR %4(s32), %8(s32)47 ; ARM: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]48 ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2REVSH [[VREGX]]49 50 $r0 = COPY %9(s32)51 ; CHECK: $r0 = COPY [[VREGR]]52 53 BX_RET 14, $noreg, implicit $r054 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r055...56---57name: test_shifts_to_revsh_commutative58# CHECK-LABEL: name: test_shifts_to_revsh_commutative59legalized: true60regBankSelected: true61selected: false62# CHECK: selected: true63registers:64 - { id: 0, class: gprb }65 - { id: 1, class: gprb }66 - { id: 2, class: gprb }67 - { id: 3, class: gprb }68 - { id: 4, class: gprb }69 - { id: 5, class: gprb }70 - { id: 6, class: gprb }71 - { id: 7, class: gprb }72 - { id: 8, class: gprb }73 - { id: 9, class: gprb }74body: |75 bb.0:76 liveins: $r077 78 %0(s32) = COPY $r079 ; ARM: [[VREGX:%[0-9]+]]:gpr = COPY $r080 ; THUMB: [[VREGX:%[0-9]+]]:rgpr = COPY $r081 82 %1(s32) = G_CONSTANT i32 2483 %2(s32) = G_SHL %0(s32), %1(s32)84 85 %3(s32) = G_CONSTANT i32 1686 %4(s32) = G_ASHR %2(s32), %3(s32)87 88 %5(s32) = G_CONSTANT i32 889 %6(s32) = G_LSHR %0(s32), %5(s32)90 91 %7(s32) = G_CONSTANT i32 25592 %8(s32) = G_AND %6(s32), %7(s32)93 94 %9(s32) = G_OR %8(s32), %4(s32)95 ; ARM: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]96 ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2REVSH [[VREGX]]97 98 $r0 = COPY %9(s32)99 ; CHECK: $r0 = COPY [[VREGR]]100 101 BX_RET 14, $noreg, implicit $r0102 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0103...104---105name: test_shifts_no_revsh_constants106# CHECK-LABEL: name: test_shifts_no_revsh_constants107legalized: true108regBankSelected: true109selected: false110# CHECK: selected: true111registers:112 - { id: 0, class: gprb }113 - { id: 1, class: gprb }114 - { id: 2, class: gprb }115 - { id: 3, class: gprb }116 - { id: 4, class: gprb }117 - { id: 5, class: gprb }118 - { id: 6, class: gprb }119 - { id: 7, class: gprb }120 - { id: 8, class: gprb }121 - { id: 9, class: gprb }122body: |123 bb.0:124 liveins: $r0125 126 %0(s32) = COPY $r0127 128 %1(s32) = G_CONSTANT i32 16 ; REVSH needs 24 here129 %2(s32) = G_SHL %0(s32), %1(s32)130 131 %3(s32) = G_CONSTANT i32 24 ; REVSH needs 16 here132 %4(s32) = G_ASHR %2(s32), %3(s32)133 134 %5(s32) = G_CONSTANT i32 8135 %6(s32) = G_LSHR %0(s32), %5(s32)136 137 %7(s32) = G_CONSTANT i32 255138 %8(s32) = G_AND %6(s32), %7(s32)139 140 %9(s32) = G_OR %4(s32), %8(s32)141 ; We don't really care how this is folded as long as it's not into a REVSH.142 ; CHECK-NOT: REVSH143 144 $r0 = COPY %9(s32)145 146 BX_RET 14, $noreg, implicit $r0147...148