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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+hwdiv -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3--- |4 define void @test_add_regs() { ret void }5 define void @test_add_fold_imm() { ret void }6 define void @test_add_fold_imm12() { ret void }7 define void @test_add_no_fold_imm() { ret void }8 9 define void @test_sub_imm_lhs() { ret void }10 define void @test_sub_imm_rhs() { ret void }11 12 define void @test_mul() { ret void }13 define void @test_mla() { ret void }14 15 define void @test_sdiv() { ret void }16 define void @test_udiv() { ret void }17...18---19name: test_add_regs20legalized: true21regBankSelected: true22selected: false23registers:24 - { id: 0, class: gprb }25 - { id: 1, class: gprb }26 - { id: 2, class: gprb }27body: |28 bb.0:29 liveins: $r0, $r130 31 ; CHECK-LABEL: name: test_add_regs32 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r033 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r134 ; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg35 ; CHECK: $r0 = COPY [[t2ADDrr]]36 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r037 %0(s32) = COPY $r038 39 %1(s32) = COPY $r140 41 %2(s32) = G_ADD %0, %142 43 $r0 = COPY %2(s32)44 45 BX_RET 14, $noreg, implicit $r046...47---48name: test_add_fold_imm49legalized: true50regBankSelected: true51selected: false52registers:53 - { id: 0, class: gprb }54 - { id: 1, class: gprb }55 - { id: 2, class: gprb }56body: |57 bb.0:58 liveins: $r059 60 ; CHECK-LABEL: name: test_add_fold_imm61 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r062 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg63 ; CHECK: $r0 = COPY [[t2ADDri]]64 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r065 %0(s32) = COPY $r066 67 %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c68 %2(s32) = G_ADD %0, %169 70 $r0 = COPY %2(s32)71 72 BX_RET 14, $noreg, implicit $r073...74---75name: test_add_fold_imm1276legalized: true77regBankSelected: true78selected: false79registers:80 - { id: 0, class: gprb }81 - { id: 1, class: gprb }82 - { id: 2, class: gprb }83body: |84 bb.0:85 liveins: $r086 87 ; CHECK-LABEL: name: test_add_fold_imm1288 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r089 ; CHECK: [[t2ADDri12_:%[0-9]+]]:rgpr = t2ADDri12 [[COPY]], 4093, 14 /* CC::al */, $noreg90 ; CHECK: $r0 = COPY [[t2ADDri12_]]91 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r092 %0(s32) = COPY $r093 94 %1(s32) = G_CONSTANT i32 409395 %2(s32) = G_ADD %0, %196 97 $r0 = COPY %2(s32)98 99 BX_RET 14, $noreg, implicit $r0100...101---102name: test_add_no_fold_imm103legalized: true104regBankSelected: true105selected: false106registers:107 - { id: 0, class: gprb }108 - { id: 1, class: gprb }109 - { id: 2, class: gprb }110body: |111 bb.0:112 liveins: $r0113 114 ; CHECK-LABEL: name: test_add_no_fold_imm115 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0116 ; CHECK: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 185470479117 ; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[t2MOVi32imm]], 14 /* CC::al */, $noreg, $noreg118 ; CHECK: $r0 = COPY [[t2ADDrr]]119 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0120 %0(s32) = COPY $r0121 122 %1(s32) = G_CONSTANT i32 185470479 ; 0x0b0e0e0f123 124 %2(s32) = G_ADD %0, %1125 126 $r0 = COPY %2(s32)127 128 BX_RET 14, $noreg, implicit $r0129...130---131name: test_sub_imm_lhs132legalized: true133regBankSelected: true134selected: false135registers:136 - { id: 0, class: gprb }137 - { id: 1, class: gprb }138 - { id: 2, class: gprb }139body: |140 bb.0:141 liveins: $r0142 143 ; CHECK-LABEL: name: test_sub_imm_lhs144 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0145 ; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg146 ; CHECK: $r0 = COPY [[t2RSBri]]147 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0148 %0(s32) = COPY $r0149 150 %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c151 %2(s32) = G_SUB %1, %0152 153 $r0 = COPY %2(s32)154 155 BX_RET 14, $noreg, implicit $r0156...157---158name: test_sub_imm_rhs159legalized: true160regBankSelected: true161selected: false162registers:163 - { id: 0, class: gprb }164 - { id: 1, class: gprb }165 - { id: 2, class: gprb }166body: |167 bb.0:168 liveins: $r0169 170 ; CHECK-LABEL: name: test_sub_imm_rhs171 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0172 ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg173 ; CHECK: $r0 = COPY [[t2SUBri]]174 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0175 %0(s32) = COPY $r0176 177 %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c178 %2(s32) = G_SUB %0, %1179 180 $r0 = COPY %2(s32)181 182 BX_RET 14, $noreg, implicit $r0183...184---185name: test_mul186legalized: true187regBankSelected: true188selected: false189registers:190 - { id: 0, class: gprb }191 - { id: 1, class: gprb }192 - { id: 2, class: gprb }193body: |194 bb.0:195 liveins: $r0, $r1196 197 ; CHECK-LABEL: name: test_mul198 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0199 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1200 ; CHECK: [[t2MUL:%[0-9]+]]:rgpr = t2MUL [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg201 ; CHECK: $r0 = COPY [[t2MUL]]202 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0203 %0(s32) = COPY $r0204 205 %1(s32) = COPY $r1206 207 %2(s32) = G_MUL %0, %1208 209 $r0 = COPY %2(s32)210 211 BX_RET 14, $noreg, implicit $r0212...213---214name: test_mla215legalized: true216regBankSelected: true217selected: false218registers:219 - { id: 0, class: gprb }220 - { id: 1, class: gprb }221 - { id: 2, class: gprb }222 - { id: 3, class: gprb }223 - { id: 4, class: gprb }224body: |225 bb.0:226 liveins: $r0, $r1, $r2227 228 ; CHECK-LABEL: name: test_mla229 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0230 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1231 ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r2232 ; CHECK: [[t2MLA:%[0-9]+]]:rgpr = t2MLA [[COPY]], [[COPY1]], [[COPY2]], 14 /* CC::al */, $noreg233 ; CHECK: $r0 = COPY [[t2MLA]]234 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0235 %0(s32) = COPY $r0236 237 %1(s32) = COPY $r1238 239 %2(s32) = COPY $r2240 241 %3(s32) = G_MUL %0, %1242 %4(s32) = G_ADD %3, %2243 244 $r0 = COPY %4(s32)245 246 BX_RET 14, $noreg, implicit $r0247...248---249name: test_sdiv250legalized: true251regBankSelected: true252selected: false253registers:254 - { id: 0, class: gprb }255 - { id: 1, class: gprb }256 - { id: 2, class: gprb }257body: |258 bb.0:259 liveins: $r0, $r1260 261 ; CHECK-LABEL: name: test_sdiv262 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0263 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1264 ; CHECK: [[t2SDIV:%[0-9]+]]:rgpr = t2SDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg265 ; CHECK: $r0 = COPY [[t2SDIV]]266 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0267 %0(s32) = COPY $r0268 269 %1(s32) = COPY $r1270 271 %2(s32) = G_SDIV %0, %1272 273 $r0 = COPY %2(s32)274 275 BX_RET 14, $noreg, implicit $r0276...277---278name: test_udiv279legalized: true280regBankSelected: true281selected: false282registers:283 - { id: 0, class: gprb }284 - { id: 1, class: gprb }285 - { id: 2, class: gprb }286body: |287 bb.0:288 liveins: $r0, $r1289 290 ; CHECK-LABEL: name: test_udiv291 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0292 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1293 ; CHECK: [[t2UDIV:%[0-9]+]]:rgpr = t2UDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg294 ; CHECK: $r0 = COPY [[t2UDIV]]295 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0296 %0(s32) = COPY $r0297 298 %1(s32) = COPY $r1299 300 %2(s32) = G_UDIV %0, %1301 302 $r0 = COPY %2(s32)303 304 BX_RET 14, $noreg, implicit $r0305...306